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Generating the MSI of PCIe

Shi Firo
Prodigy 110 points

Hello,

         Recently I have been studying the PCIE between two C6678 DSPs. I have configured one C6678 as RC and another C6678 as EP. 

        My program is based on the PCIe example project provided in the pdk for the C6678 but am attempting to use  MSI functionality into it to improve on the handshake technique used .In other words,I would like to use MSI interrupts on both sides.Before EP send data to RC,it send a MSI interrupt,this process has been achieved.But I also want to generate a MSI on RC ,then EP can use HWI ISR to receive the data,and use DMA to transfer the data.

      I check many posts on the community,but cann't find the answer in detail.so here are my questions:(1).can RC generate a MSI interrupt?(2).if yes,How can I generate a MSI interrupt?please tell me the concrete detail just like this as follows.( the following content is about the process how to setup the EP for generateing a MSI).   If answer is no,please also tell me other methods to genetate a interrupt on RC side .By receiving the interrupt,EP can use ISR to transfer the data.

if you set BAR0 in RC as 0x70000000 (PCIe address over the PCIe link as you defined) and you should setup the outbound translation in EP to use the same PCIe address (0x70000000) over the link. Then you can write 0x0 to the PCIe data space (e.g. write 0x0 to 0x60000054 in EP). The write will be translated to 0x70000054 over the PCIe link and could be accepted by BAR0 in RC, which is 0x70000000.  SInce BAR0 is mapped to Application Registers region (from 0x21800000), the writing to 0x70000054 (from EP) will be targeted to 0x21800054 in RC and the MSI_IRQ in RC will be written into 0x0, which will trigger MSI_0 in the RC.----------------said by Steven Ji

I am look forward to your help!

THX

Shi

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 110 points

    Hi,Ganapathi.

         Actually,I already read these threads many times before you give ,maybe I still don't understand the content .From them,I also can't get something I want to know. I think they just discuss about how to generate MSI interrupt from EP to RC,this process I have achieved it. So please tell me the opposite process from RC to EP directly,specially the generation of MSI on RC side.In EP,I use HWI to response to the MSI.

        Of course,I also have some questions ,I hope you can explain them to me.

    (1).from the thread :http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/202251.aspx

    /*Move Outbound Translation to trigger MSI; 0x7000_0000 */
    pcieObTransCfg(0x70000000, PCIE_OB_HI_ADDR_S, PCIE_OB_REGION_S);

    System_printf("Interrupt Sent\n");
    *((volatile uint32_t *) 0x60000054) = 0x0;

    /*Move Outbound Translation back to sending data; 0x9000_0000*/
    pcieObTransCfg(0x90000000, PCIE_OB_HI_ADDR_S, PCIE_OB_REGION_S);

       Previously I also did it like this,but just from EP to RC. but  it did not work when I did it from RC to EP just like this:

    /*Move Outbound Translation to trigger MSI; */
    pcieObTransCfg(0x90000000, PCIE_OB_HI_ADDR_S, PCIE_OB_REGION_S);

    System_printf("Interrupt Sent\n");
    *((volatile uint32_t *) 0x60000054) = 0x0;

    /*Move Outbound Translation back to sending data;*/
    pcieObTransCfg(0x70000000, PCIE_OB_HI_ADDR_S, PCIE_OB_REGION_S);

    Now I still  don't know why it does't work? Is the address of MSI_IRQ wrong ?

    (2) From the thread:http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/166202.aspx

    just as steven Ji said ,we can set bit 0 in MSI0_IRQ_STATUS_RAW to generate the MSI_0 interrupt,does it have a relationship with MSI_IRQ.what does it mean for debug purposes?

    (3) From the section 2.13.3 in TI's pcie User guide,the sentence "The behavior is similar to generation and reception of MSI interrupts in RC mode except for the fact that this functionality is enabled in EP mode as well."

    In my view,it tell RC can also generate the MSI interrupt ,but " except for the fact that this functionality is enabled in EP mode as well" how to understand?

    just as the user guide say,"The RC device can perform a memory write into the MSI IRQ register over the PCIe 

    link to generate one of 32 EP interrupts." I just  perform a memory write into the MSI IRQ ,and I also clean up the interrupt status in the HWI ISR on EP side in order to avoid the accumulation multiple writes to the same MSI vector.

    Actually I just want to the answer which is yes or no,if yes ,just tell me .

    Sincerely.

    THX

    SHI

  • 0 in reply to Shi Firo
    TI__Genius 12065 points

    SHI,

    As what mentioned in TI PCIe user guide, the MSI generation from RC to EP is not supported based on PCIe standard specification. But the PCIe module in TI C66x devices gives you more flexibility to generate MSI from RC. Please do not assume the same feature is applicable to other non-C66x PCIe RC device.

    1. No matter which side (RC or EP) generates the MSI, the idea is the same: one side needs to generate one memory write transaction which could write the MSI vector value to the MSI_IRQ register on the other side.

    For example, if you want to generate MSI_0 from RC to EP:

    a. Make sure MSI_EN bit is set in MSI_CAP register on RC (which should be set on EP as well if EP generates MSI)

    b. Make sure the corresponding bits is set in MSIn_IRQ_EN_SET register on EP, such as bit 0 is set in MSI0_IRQ_EN_SET if MSI_0 is going to be used

    c. Make sure RC could write to MSI_IRQ register on EP correctly. 

        OB_XLT_EN bit is enabled in CMD_STATUS in RC;

        OB_ENABLEn is set in OB_OFFSET_INDEXn register in RC and address after translation matches with BAR0 in EP (BAR0 is fixed mapping to Application Register space in C66x PCIe module for both RC and EP);

        HWI/ISR setup is correct on EP to generate interrupt to CPU when MSI is recevied (double check event number and mapping).

    2. The debug purpose of MSIn_IRQ_STATUS_RAW means, if you do not have any external device to generate MSI to the local device, you could still manually set bits in MSIn_IRQ_STATUS_RAW register to simulate the generation of MSI by the local device itself. The corresponding bit in MSIn_IRQ_STATUS will be set and the HWI/ISR should be triggered as well. It gives the user the capability to test the MSI HWI/ISR setup in the local device without external device support. But it is not what will be used in the real application, so it is just for debug purpose.

    3. Yes. RC could generate MSI to EP in C66x PCIe module. "the functionality is enabled in EP mode as well" means the steps I mentioned in #1 above that several steps need to be done on EP side (also on RC side).

    I think you are close to make this feature work. Hope the key points mentioned above could help.