SRIO Mulitcore Questions C6678

Hi Lawrence,

The example was written to use 4 cores on the device. In addition to changing the definition of the number of cores being used, some other modifications will be needed in the driver configuration, as you mentioned. 

I have not done this myself, but some areas to consider are:

In the 'test_multicore' function:

• Adding the new device IDs to the 'coreDeviceID' array

In the 'multicoreTestTask' function:

• Number of RX buffers
• The 'coreToQueueSelector' array
• Number of TX buffers

Let us know if that is able to help them make progress.

Thanks,

Clinton

Cllinton,

Customer has tried with both C6678 and C6674.  On the C6674:

The number of cores is set to 4 as needed.

The device IDs are set and seem to work (due to them being routed appropriately).

The example has the number of Rx buffers, Tx buffers, and coreToQueueSelector array assigned in what looks like an appropriate manner. Do I have to change them in some way?
coreToQueueSelector[] = 704, 705, 706, 707. num buffers are each set to 4.


What would cause only the first 2 cores to initialize to work and not the other 2?

For the C6678 setup is similar but with 8 cores being set.  In both situation only half the cores works with SRIO. 

For the C6678 setup it can be cores 0-3 or cores 4-7, but always just thhe first 4 cores working and the last 4 does not..  In the C6674 devicit will be the first 2 cores working and not the last 2 cores.

Regards,

Lawrence

Hi Lawrence,

To clarify, when you use the PDK multicore loopback example for the c6678 on the c6674 device, with the number of cores set to 4, only 2 cores are initialized and you receive an error? If you change the number of cores to 2 in the example, it then works on the c6674?

I would have thought that since the example is written for 4 cores, that it would work for the c6674 (I currently do not have a board with a c6674 device to test this myself). I'm going to do some more research  as to why you're seeing this behavior on the c6674 with the example and how to extend the example from 4 cores to 8 cores on the c6678.

Thanks,

Clinton

Hi Lawrence,

Can the customer provide the console dumps from the failing test runs? Can you also find out what version of BIOS MCSDK they are using?

Thanks,

Clinton

Hi,

I think multiple older issues are getting mashed together here. Let me state the issue in it's current form:

I have the multicore example on a C6678 modified to attempt to use all 8 cores instead of just 4. The current issue is that core 7 fails upon binding the socket, while all the other cores appear to have initialized appropriately. The changes I've made are as followed:

-In the cfg file I increased the size of the sharedmem for IPC to work.
-In cfg file, also increased the number of cores for IPC "MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", ..."
-Expanded the "CoreDeviceID" array to have 8 entries instead of 4. "coreDeviceID[0] = DEVICE_ID1_16BIT;"
-Expanded the "coreToQueueSelector" array to have 8 instead of 4 queues.
-In device_srio_loopback.c, added additional "CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);" and "CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);" functions for the four new cores.
-In device_srio_loopback.c, have "CSL_SRIO_SetNormalMode(hSrio, 0);" for each core.
-In device_srio_loopback.c, expanded the TLM/BRR functions to be as seen below:
CSL_SRIO_SetDeviceIDCSR (hSrio, DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);

/* Enable TLM Base Routing Information for Maintainance Requests & ensure that
* the BRR's can be used by all the ports. */
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 1, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 2, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 3, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 0, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 1, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 2, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 3, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 2, 0, 1, 1, 0);

/* Configure the Base Routing Register to ensure that all packets matching the
* Device Identifier & the Secondary Device Id are admitted. */
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 1, DEVICE_ID2_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 2, DEVICE_ID3_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 3, DEVICE_ID4_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 0, DEVICE_ID2_8BIT, 0xFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 1, DEVICE_ID5_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 2, DEVICE_ID6_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 3, DEVICE_ID7_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 2, 0, DEVICE_ID8_16BIT, 0xFFFF);

Do you see any issues in this? Did I miss something? Am I not setting the TLM/BRRs correctly? Any thoughts?

Thanks in advance,

-Dan

Dan Skehan said:

The current issue is that core 7 fails upon binding the socket, while all the other cores appear to have initialized appropriately.

What does it mean that core 7 fails exactly?  All other cores are able to open/bind a socket?  Need more description.

Dan Skehan said:

-In device_srio_loopback.c, added additional "CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);" and "CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);" functions for the four new cores.

This would not need to be rerun per core.  Once the serdes are setup, they are setup and can be used by any core.  It is possible that if you are re-initializing the serdes in any way, you could be causing the link to have to re-initialize via the SRIO protocol, and that shouldn't be done.

There should be no difference between core's setup.  If one works, any of them should be able to work using the same queues and ports.  For test puposes, forget about the deviceIDs and use the same one from a working core as on the core 7. 

Regards,

Travis

Hi,

First I would like to repeat "I have the multicore example on a C6678 modified to attempt to use all 8 cores instead of just 4."

tscheck said:

What does it mean that core 7 fails exactly?  All other cores are able to open/bind a socket?  Need more description.

I mean core 7 printed out "Error: socket1 bind failed". Just like in the example...

tscheck said:

This would not need to be rerun per core.  Once the serdes are setup, they are setup and can be used by any core.  It is possible that if you are re-initializing the serdes in any way, you could be causing the link to have to re-initialize via the SRIO protocol, and that shouldn't be done.

...The example only performs the init on core 0. There is no rerunning of this portion of the code.

Any who. I got the code working. I have no idea what the issue was. I deleted the Debug folder and rebuilt then everything worked fine. Apparently CCS's clean does not work so well...

Hi Dan,

Following up to confirm you were able to get the example working for your use case (8 cores), is this correct? Let us know if there are any open questions regarding this issue.

Thanks,

Clinton