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ARM kernel not executing Linux

Other Parts Discussed in Thread: 66AK2H12

Dear Support Team

I'm trying to understand if (and how) I can use a 66AK2H12 divided into two parts:

- Two ARM cores executing the Keystone II Linux and

- Two ARM cores executing simple RT controlling algorithms (no Linux OS, just quick "main loops").

I found that there is a good support for ARM <-> DSP interaction, is there the same situation for ARM (executing Linux) <-> ARM (not executing Linux) interaction? Can I find any examples on how this can be achieved?

Thank You for Your Support

/Peter Lööf

  • Hi,

    Thank you for the post.

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    It may be possible. Please refer below post.

    http://e2e.ti.com/support/embedded/linux/f/354/p/355151/1253881.aspx#1253881

    If the SMP Liunux kernel is used the standard IPC would help to communicate between ARM cores. 

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/309273/1093670.aspx#1093670

  • Hello Rajasekaran,

    Thank you for your quick response. My problem is that I'm not going to use Linux in all ARM's, just two of them. In the other two, I'm not going to use any OS, only build a simple loop-based program.

    What I've read about DSP:s is that they can be loaded, checked status etc via the mpmcl command.


    So, what I would like to do is handle the ARM cores that are not executing Linux in the same way.


    Is this possible?

    Thank You

    /Peter

    Additional question:

    Would it be possible to run the TI-RTOS (SYS/BIOS) on the two ARM core's that don't run Linux?

  • Hi Peter,

    It should be possible. Please refer the ARM(spruhj3) and DSP(sprugy5) boot loader user guide for more information.

    On device power up with ARM as the boot master, all secondary ARM cores are held in reset. When a secondary ARM core is needed, any active core may load code for the secondary core to the execution address, write the execution address to the boot magic register, generate an IPC interrupt to the core, and take the core out of reset. The secondary core will then come out of reset and begin executing the code provided to it.

    On device power up with ARM as the boot master, all DSP cores perform basic initialization and then enter the idle state. When a DSP is needed, any active core may load code from the DSP core to the execution address, write the execution address to the boot magic address, and generate an IPC interrupt to the core. The DSP will then come out of the idle stat and begin executing the code provided to it.

    Thank you.

  • Hi Peter,

    I missed the additional question,

    Currently there is no SYS/BIOS support on A15 with MCSDK 3.x release for K2H. We only support Linux now.

    Thank you.