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66AK2H12/06 USB3.0 GHWPARAMSn register

RY9983
Guru 10570 points
Other Parts Discussed in Thread: 66AK2H12


Hello,
I am using 66AK2H12/06 USB3.0 interface.
There is no detail in the fields of GHWPARAMSn.

Can you provide me the datail or any information about following fields:

USB3(spruhj7) 3.2.8.16 GHWPARAMS1
30bit USB3_RM_OPT_FEATURES
28bit USB3_RAM_BUS_CLKS_SYNC
27bit USB3_MAC_RAM_CLKS_SYNC
26bit USB3_MAC_PHY_CLKS_SYNC
14-12bit USB3_ASPACEWIDTH
11-9bit USB3_REQINFOWIDTH
8-6bit USB3_DATAINFOWIDTH

USB3(spruhj7) 3.2.8.20 GHWPARAMS5
27-22bit USB3_DFQ_FIFO_DEPTH
21-16bit USB3_DWQ_FIFO_DEPTH
15-10bit USB3_TXQ_FIFO_DEPTH
9-4bit USB3_RXQ_FIFO_DEPTH
3-0bit USB3_BMU_BUSGM_DEPTH

USB3(spruhj7) 3.2.8.21 GHWPARAMS6
7bit USB3_EN_FPGA
5-0bit USB3_PSQ_FIFO_DEPTH

Best regards, RY

  • 0
    TI__Guru* 81335 points

    Hi,

    We are working on your post. We will get back to you. Thank you for your patience.

  • 0
    TI__Intellectual 1805 points

    RY,

    Can you clarify on why you need those register fields, and how will you use those information in your SW?

    I have been looking for the details of those register fields for you. So far, it seems to me that they are all HW configuration parameters, which are used to control the generation of the controller system. If needed, I will have to contact our design team for more details.

    Regards!
    Wen

  • 0
    TI__Intellectual 1805 points

    RY,

    Here is what I get. As I said, those registers fields are mainly for HW configuration parameters, and are not intended for SW to use.

    GHWPARAMS1

    28bit USB3_RAM_BUS_CLKS_SYNC
    27bit USB3_MAC_RAM_CLKS_SYNC
    26bit USB3_MAC_PHY_CLKS_SYNC 


    These bits shows whether specific CLKS synchronization process being added between two clock domains.


    14-12bit USB3_ASPACEWIDTH
    11-9bit USB3_REQINFOWIDTH
    8-6bit USB3_DATAINFOWIDTH

    These bits tell what the bus interface width are. For example, the USB3_ASPACEWIDTH=4  => the write/read request address space bus’s width is [3:0].



    GHWPARAMS5
    27-22bit USB3_DFQ_FIFO_DEPTH
    21-16bit USB3_DWQ_FIFO_DEPTH
    15-10bit USB3_TXQ_FIFO_DEPTH
    9-4bit USB3_RXQ_FIFO_DEPTH
    3-0bit USB3_BMU_BUSGM_DEPTH

    GHWPARAMS6
    5-0bit USB3_PSQ_FIFO_DEPTH

    These parameters shows some depth of internal queues inside the RAM0. The depth are fixed, and the queue are managed by hardware <the Buffer Manage Unit – BMU>. For example, BMU Descriptor Fetch Request Queue Depth (DFQ_FIFO_DEPTH), BMU Protocol Status Queue Depth (PSQ_FIFO_DEPTH), BMU Descriptor Write Queue (DWQ_FIFO_DEPTH),  Rx Info Queue Depth (RIQ_FIFO_DEPTH), etc.



    GHWPARAMS6
    7bit USB3_EN_FPGA 

    This bit indicates whether the current implementation is on a FPGA platform. It is mainly for HW validation purpose or driver development on a FPGA platform. It is not for silicon driver development.

    Regards!
    Wen