Pcie boot problem in arm of K2H

eager hsu

hi , I want to load image(uboot and kernel) to K2H that is a PCIe EP and boot it. I can load uboot to MSM now.
but I meet some problem.

I see the Doc say :

PCI Express (PCIe) Boot
The PCIe boot mode transfers a boot image via the PCIe interface into MSMC for
execution. This image must be in Blob Format. The bootloader queries the device boot
configuration pins for set up of the BARs, windows, and their sizes as desired to provide
memory access to the host. Additional information about these configurations and
other registers can be found in the device-specific data manual.
After configuration of the peripheral, the ARM core executes a WFI instruction that
causes the ARM to suspend execution waiting for an interrupt. While the ARM is
suspended, the PCIe host can write the boot image into MSMC. After the image is
written, the PCIe host must write the execution starting address of the image to the host
boot data address register.
MSI interrupts are enabled and routed to break out of the suspended state.

1.
I see default of address DSP_BOOT_ADDR0 (0x02620040) is 20B00001.
can you tell me the format of this field?
it should be not general address field.
it's bit 0 is always 1 and bit 2-9 is always 0.

2.
and another problem about MSI interrupt. I see PCIe Doc has two address used by MSI.

100h MSI0_IRQ_STATUS_RAW MSI
104h MSI0_IRQ_STATUS MSI
108h MSI0_IRQ_ENABLE_SET MSI
10Ch MSI0_IRQ_ENABLE_CLR MSI
110h MSI1_IRQ_STATUS_RAW MSI

and
1050h MSI_CAP MSI
1054h MSI_LOW32 MSI
1058h MSI_UP32 MSI
105Ch MSI_DATA MSI
should I use which address to trigger boot flow.

3. finally problem that ARM core must excute WFI instruction.
when K2H use PCIe boot as a EP, ARM is suspended?
if it is not, how I should let arm to execute WFI instruction?

thanks for your help.

over 9 years ago

0 eager hsu over 9 years ago

Intellectual 260 points

about question 1.

should ARM use 0xc5a_d000 (Arm boot magic address) to set boot address?

if it is right. you can ignore question 1.

and question 2

1050h MSI_CAP MSI
1054h MSI_LOW32 MSI
1058h MSI_UP32 MSI
105Ch MSI_DATA MSI

is it used for RC?

thanks.

0 Raja over 9 years ago in reply to eager hsu

TI__Guru* 81335 points

Hi Eager,

Q1: Your understanding on ARM core boot magic address is correct.

0xc5a_d000 Arm boot magic address, core 0

0xc5a_d004 Arm boot magic address, core 1

0xc5a_d008 Arm boot magic address, core 2

0xc5a_d00c Arm boot magic address, core 3

Q2: We are wokring with PCIe expert on MSI interrupt. We will get back to you.

Thank you.

0 Ganapathi Dhandapani95 over 9 years ago in reply to Raja

TI__Mastermind 28085 points

Hi Eager,

In PCI Express base specifications, root complex ports only receive interrupts. There is no mechanism to generate interrupts from RC port to EP mode as per PCIe specification. However, the PCIESS does support generation of interrupts from RC to EP. The behavior is similar to generation and reception of MSI interrupts in RC mode except for the fact that this functionality is enabled in EP mode as well.

Please refer section 2.14.3 Interrupt Generation in RC Mode on pcie user guide.

Thanks,

0 eager hsu over 9 years ago in reply to Ganapathi Dhandapani95

Intellectual 260 points

Dear Ganapathi

in fact, I have set the MSI interrupt to arm of k2h before.

I set 54h (MSI_IRQ) value 0x0 to generate MSI interrupt vector 0.

then check the value of MSI0_IRQ_STATUS_RAW is 0x1 and value of MSI0_IRQ_STATUS is 0x1.

but arm do not boot.

I have check u-boot image is in MSM and the value of 0xc5a_d000 (Arm boot magic address) is set to MSM(0xc00 0000) by CCS.

the boot Doc say that arm should boot, but it do not.

so I want your help to check which steps I miss.

question 2 check that I should use 54h (MSI_IRQ) or another register to trigger MSI.

question 3 check the below.

when K2H use PCIe boot as a EP, ARM is suspended? and if it is not, how I should let arm to execute WFI instruction?

thank for your help.

0 lding over 9 years ago in reply to eager hsu

TI__Guru* 95265 points

There is a wiki talking about how to run u-boot through CCS

http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS

So, this means the u-boot is a flat binary file. The wiki use CCS to load, set Program counter then run. For you, you PCIE RC needs some application code to write the u-boot into MSMC of the ARM core, PCIE EP side. Then, you need to set the ARM code boot start address like setting PC in CCS.

Last, you need to send an interrupt to ARM core to let it running via PCIE. I need to check how it works.

Regards, Eric

0 lding over 9 years ago in reply to lding

TI__Guru* 95265 points

We typically support both MSI and the legacy A-D interrupts.

The RC can poke these by mapping a window into the EP application registers. To poke the MSI you poke the MSI_IRQ (I think there are 8 different bits you can use, but check the doc), to clean up either the RC or EP pokes the MSI_CLR register, also in the application register space.

The legacy interrupts are also in the application register space, but there is only 1 bit you poke to generate the interrupt (and one register for each type). Each interrupt also has a clear register that either the RC or EP can use to clear the interrupt after it is sent. If you don’t clear it then you can’t send a second interrupt (of the same type)

Before ARM jump out, it is executing WFI in bootrom.

Regards, Eric

0 eager hsu over 9 years ago in reply to lding

Intellectual 260 points

Dear Iding

thanks for your information.

I find the problem is uboot image must load to 0xc001000, not 0xc000000

I can load uboot and boot it through pcie now.

thanks.

0 Raja over 9 years ago in reply to eager hsu

TI__Guru* 81335 points

Hi Eager,

Thank you for the update.

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Pcie boot problem in arm of K2H