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Why is c6671 getting hot when POR is asserted?

Hello,

I started to test my board which has three c6671s.

There is no code until now because I am testing power and clock part.

I turned on all kinds of power I use and clock driver-cdce62005.

When I turned only powers, the current consumption of smart reflex power(1v) of each c6671 was about 1A. 

When I turned powers and clock drivers, the current consumption of smart reflex power of each c6671 was about 2A.

I check current consumption by System Dashboard window of 'Fusion Digital Power Designer' software.

The POR, RESETFULL, RESET signals were still low.

Is it normal that current consumption increases when reset signals were low?

  • Yes, it's normal to have a rise in current draw on CVdd when the device is HW reset when compared to an idle state.

    When in POR the device is actively resetting device states and attempting lock onto clocks etc.  This consumes more power than the device simply being in an idle state.

    Best Regards,

    Chad