hi, all
In the SPRS866E, it's say that 4MB L2 Cache Memory Shared by All ARM CorePacs. but I can't find any memory map of ARM L2 in the Table 6-1. It only have DSP corepac0-7 L2 memory map.
Thank you !!!
Best Regars
Gavin
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hi, all
In the SPRS866E, it's say that 4MB L2 Cache Memory Shared by All ARM CorePacs. but I can't find any memory map of ARM L2 in the Table 6-1. It only have DSP corepac0-7 L2 memory map.
Thank you !!!
Best Regars
Gavin
hi, Rajasekaran
Thank you for you clarification. I have some further questions to consult you.
As you describle that I can not access the arm L2 memory, if I program ARM code, I can only access DDR3A ,DDR3B or share memory. and when I debug the code, the code only be loaded to these memory to run.
And I wonder that what usage the ARM L2 has, because we can not access it.
Best Regards
Gaving
Please refer Memory Management Unit of ARM core Technical reference manual for L2 usage. The TRM shall be downloaded from ARM website(ARM® Cortex®-A15 MPCore™ Processor, Technical Reference Manual).
http://infocenter.arm.com/help/index.jsp
The ARM A15 is based ARMv7-A architecture. Please find the ARM® Architecture Reference Manual(ARMv7-A).
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html
Thank you.