C6657 CIC prioritization

Hi Kazu,
The CIC provides hardware to perform this prioritization with a given scheme so that software does not have to do this. Please refer 1.3.5 Prioritization of KeyStone Architecture Chip Interrupt Controller (CIC) User Guide(SPRUGW4A).

The Global Prioritized Index Register(offset 0x080) and Host Interrupt Prioritized Index Registers(offset 0x900~) are just status registers described in CIC user guide.

Thank you.

Hello Rajasekaran,

Thank you for your reply. Yes, there is a description below in the section.

The next stage of the CIC is prioritization. Prioritization may not be implemented in
all of the CICs in KeyStone devices. Please refer to the device-specific data manual for
details.

As mentioned before, I can't find these registers in data manual. I seem CIC of C6657 doesn't have prioritization. But actually, it has these registers and a functionality of prioritization written CIC UG, doesn't it?

Regards,
Kazu

Hello Rajasekaran,

Would it be possible for you to tell me that the following registers for the prioritization are implemented on CICx of C6657? Please give me more information.
- Control Register (0x004)
- Global Prioritized index Register (0x800~)
- Host Interrupt Prioritized Index Registers (0x900~)

Regards,
Kazu

Hi Kazu,
Apologize for the confusion. From my understanding is that we can go ahead with C6657 data manual because the CIC user guide is shared across all the keystone devices.

Also, I have requested factory team to comment on this. Thank you for your patience.

Hello Rajasekaran,

Were you able to confirm about the prioritization? I tried confirming it. I think it's not working. I mapped the system interrupt 10 and 11 to the channel/host interrupt 3 by CH_MAP_REG. Then I enabled the system interrupt 10 and 11 by ENABLE_SET_INDEX_REG. I also enabled the channel/host interrupt 3 by HINT_ENABLE_SET_INDEX_REG. After that I triggered the system interrupt 10 and 11 by STATUS_SET_INDEX_REG. So I could see occurring one interrupt and two statuses from RAW_STATUS_REG. But I could not see a behavior as the prioritization from Host Interrupt Prioritized Index Registers and Global Prioritized Index Register. These prioritization registers were zero during ISR when I saw memory browser of CCS. Please give me some advices.

Regards,
Kazu

Hello Rajasekaran,

I appreciate your support. I read Global Prioritized Index Register, Host Interrupt Prioritized Index Register 10 and 11 into temporal buffers during ISR. Each of them had a certain value (not zero), but I could not see a value as the prioritization. Please give me any  information.

Regards,
Kazu

Hi Kazu,
I am following up our factory team, we will get back to you. Thank you for your patience.