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Low Priority Accumulator Queue Configuration.

rogue processor
Prodigy 110 points

Hi,

I had a query regarding the low priority accumulation queues.

I am using c6670 , now I want to enable low priority accumulation for 4 queues(I understand upto 32 queues can be monitored this way, I want just 4).

Now each queue is supposed to belong to different cores, s in case say I push a descriptor with psinfo containing the core number, I want to check this in the ISR which will be called in all cores. Depending on the core number I will either execute the required functionality on a particular core otherwise I will return from that particular ISR.

What I wanted to confirm is, do I have to acknowledge and EOI on each core separately?

I understand that I need to map this accumulator channel event number corresponding to low priority to a interrupt vector id which is unique 12 interrupt for all the cores. So it seems I need to acknowledge the interrupt on all the core?

Is my understanding correct so far.

Thanks in advance.

  • 0
    TI__Guru* 81335 points
    Hi Rogue,
    We are working on this post and get back to you. Thank you for your patience.
  • 0 in reply to Raja
    Prodigy 110 points

    Hi Raja,

    Any update on this will be greatly appreciated.

    Thanks in advance.

  • 0 in reply to rogue processor
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.


    Yes, your understanding is correct. You can find the 0-511(512 Queues) low priority accumulation queues. It is separated 16 channels and each channel having 32 queues.
    Go through the section "Table 5-1 Queue Map for Keystone I" at the Multicore Navigator User Guide.
    The interrupt name and correspond DSP event id can find in the "Table 5-5 Low Priority Queue Mapping" at the Multicore Navigator User Guide

    Once the host has processed all list buffer pages for all the channels associated with the interrupt, it must then perform an EOI by writing the correct value to the INTD EOI register.

    Find the more detail in the section "4.4.1.2 End Of Interrupt (EOI) Register" and "Table 4-73 EOI Register Field Descriptions" at the Multicore Navigator User Guide.

    Thanks & Regards,

    Sivaraj K

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