SRIO is not working properly in the condition that DSP core frequency is high

Hi,

Have you test the SRIO transfer between C6678 and C6455 devices without SRIO switch at 1GHz?

You mentioned 6678 can read and write the looped back packages from its own by switch. It is PHY level loop-back test (internally looped back) or eternal loop-back(looped back externally using an external SRIO switch).

Thanks,

1. I cannot directly connect 6678 with 6455. So I cannot test 6678 and 6455 device without SRIO switch.
2. I had tried both PHY level loopback and eternal loopback by using switch. They are all working.

Thanks.

Hi,

C6678 eternal loop-back(looped back externally using an external SRIO switch) mode woks means SRIO switch drive the data properly. Try to test the same on C6455 device.

Both device Specification compliant revisions are different, C6678 support up to 5Gpbs line rate but C6455 support limit is 3.125 Gpbs. So provide the SRIO configuration detail on both C6678 and C6455 devices(SRIO reference clock, line rate, MPY value).

Thanks,

6645 can perform external loop back successfully too.
Configuration on 6678:
SRIO reference clock: 312.5MHz
line rate: 1.25Gbps
MPY value :
CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

/* Configure the SRIO SERDES Receive Configuration. */
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404B5);
CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x004404B5);
CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x004404B5);
CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x004404B5);

/* Configure the SRIO SERDES Transmit Configuration. */
CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807B5);
CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x001807B5);
CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001807B5);
CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x001807B5);

Configuration on 6455:
SRIO reference clock: 125 MHz
line rate: 1.25Gbps
MPY value:
wdata_SERDES_CFGn_CNTL = CSL_FMKT(SRIO_SERDES_CFG_CNTL_MPY,10); //x10. 1.25Gbps, half rate
wdata_SERDES_CFGRXn_CNTL = CSL_FMKT(SRIO_SERDES_CFGRX_CNTL_RATE,HALF);
wdata_SERDES_CFGTXn_CNTL = CSL_FMKT(SRIO_SERDES_CFGTX_CNTL_RATE,HALF);


Regards
Xining

Hi,

Thanks for your detailed information.

C6455 SRIO configuration is fine for 125 MHz reference clock, MPY 10, Half Rate at 1.25Gbps line rate. As per the Table 8. "Frequency Range versus MPY Value" on SRIO user guide.

C6678 SRIO configuration you selected wrong MPY value. Refer Table 3-7 Frequency Range versus MPY Value on C6678 SRIO user guide to select the proper MPY value based on your reference clock and line rate.

Thanks,

Hi,

Thanks for your detailed information. 

C6455 and C6678 SRIO configuration is fine for your reference clock, MPY, Rate at 1.25Gbps line rate. As per the "Frequency Range versus MPY Value" on SRIO user guide.

Have you using the same SRIO configuration for PLL by-pass mode?

Please try to test the C6455 eternal loop-back(looped back externally using an external SRIO switch) mode.

Thanks,

Yes, I did. It works fine. We did not change SRIO and other configuration when we enable the PLL.

You said for 6678, my MPY is wrong. I do not get it.

CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);  means MPY is 8.

CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404B5); means receiving data rate is eight rate.

CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807B5); means trasmitting data rate is eight rate.

From the table 3-7 in the 6678 SRIO manual, it shows that for the RefClk 312.5Mhz it we want to get 1.25Gbps, it should be MPY=8, data rate=eighth. That is what I exactly programmed.

Regards

Xining Yu

Thanks for your Ganapathi