Suppose an SRIO flow gets XOFF'ed, and then a Direct I/O operation using that flow becomes "ready" from the DSP's perspective (either because LSUn_REG0 through LSUn_REG5 are written, or a previously triggered transfer moves from shadow LSU registers to the front of the LSU's queue). Is there any delay before LSU_STAT_REGn shows the new transaction as failed with completion code 2?