errors in the SRIO TMS320C6678

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Hi,

Please provide the more information for your test setup. Have you getting error in 4x lane mode configuration?

Have you using TI provide SRIO example code for your testing?

Thanks,

Are you using EVM or custom board? MCSDK version used?

Hi, Ganapathi!

We have develop and manufactured custom board. The board has a number of switches and subscribes. We see the problem only in a port of switch which is connected to the DSP. The switch is always connected to the processor in mode 4x, ie the port is configured in mode 4x (at a speed 3,125 Gb/s). We also see the problem when the port is operating at the speed 2,5 Gb/s. 

The problem looks like a automatically force downgrade the port of switch in the mode 1x, at that the counter BER (bit error rate) in a status register of the lane1 and lane 2 of the switch are in maximum value, but a value of the counter BER in a status register of the lane 0 and lane 3 are zero.

So this is working project which is based on an examples projects by TI.

Board platform - custom board

Processor tms320c6678 ver. 1

Work station with OS Ubuntu 13.04 x64

 

Code Composer Studio Version: 5.5.0.00077

compiler c6000_7.4

 

Used libraries:

Inter-processor Communication 1.25.3.15

MCSDK 2.1.2.6

MCSDK PDK TMS320C6678

NDK 2.21.1.38

SYS/BIOS 6.35.4.50

 

 

RTSC/XDCtools 3.25.03.72

Plug-in version: 3.25.3.72

 

RTSC/XDCtools 3.25.04.88

Plug-in version: 3.25.4.88

 

RTSC/XDCtools 3.25.04.88

Plug-in version: 3.25.4.88

Thanks

Hi, Ganapathi!
Our SRIO settings and method of configuration:


//SRIO GBaud per lane: 3.125, RefClk (MHz): 312.5
/*
srio_config.srio_rate = c66xu::kSrioRateHalf;

config.is_loopback_enabled = false;
kSrioMultiplyFactor = 5;

enum SrioRate {
kSrioRateFull = 0,
kSrioRateHalf = 1,
kSrioRateQuater = 2,
kSrioRateReserved = 3
};
*/

Srio_DrvHandle InitSrio(const MasterConfig &config) {
// init srio device
c66xu::SrioDeviceConfig srio_config;
srio_config.is_loopback_enabled = config.is_loopback_enabled;
srio_config.pll_multiply_factor = kSrioMultiplyFactor;
srio_config.srio_rate = c66xu::kSrioRateHalf;
srio_config.path_mode = c66xu::kSrioMode1port4x;
srio_config.device_id = config.device_id;
srio_config.num_port_checks = 1000;
c66xu::InitSrioDevice(srio_config);
// init driver
Srio_DrvHandle srio_driver =
c66xu::InitSrioDriver(
reinterpret_cast<uint32_t *>(kSrioMessageBufferAddress),
kSrioMessageBufferSize);
return srio_driver;
}



void InitSrioDevice(const SrioDeviceConfig &config) {
// store srio config for reset
srio_device_config = config;
// get srio handle
srio_handle = CSL_SRIO_Open(kDefaultSrioInstanceNumber);
if (srio_handle == NULL) {
Raise(kErrorSrioOpen);
return;
}
// code to disable SRIO reset isolation
// srio will reset when the device resets
if (CSL_PSC_isModuleResetIsolationEnabled(CSL_PSC_LPSC_SRIO)) {
CSL_PSC_disableModuleResetIsolation(CSL_PSC_LPSC_SRIO);
}
// disable controller
internal::DisableSrioDevice(srio_handle);
// set boot complete to be 0; we are not done with the initialization
CSL_SRIO_SetBootComplete(srio_handle, 0);
// enable Controller
internal::EnableSrioDevice(srio_handle);
// set loopback mode
if (config.is_loopback_enabled) {
for (int i = 0; i < kSrioPortCount; ++i) {
CSL_SRIO_SetLoopbackMode(srio_handle, i);
}
}
// enable Automatic Priority Promotion of response packets
// unknown use
CSL_SRIO_EnableAutomaticPriorityPromotion(srio_handle);
// Set the SRIO Prescalar select to operate in the range of 313.2 to 626.4
CSL_SRIO_SetPrescalarSelect(srio_handle, 6);
// Unlock the Boot Configuration Kicker
// allow the Boot configuration MMR registers to be come writeable
CSL_BootCfgUnlockKicker();
// set PLL according to config
CSL_BootCfgSetSRIOSERDESConfigPLL(internal::FormSerdesConfigPllValue(config));

// Configure the SRIO SERDES Rx Tx
uint32_t serdes_config_rx_value = internal::FormSerdesConfigRxValue(config);
uint32_t serdes_config_tx_value = internal::FormSerdesConfigTxValue(config);
for (int i = 0; i < kSrioPortCount; ++i) {
CSL_BootCfgSetSRIOSERDESRxConfig(i, serdes_config_rx_value);
CSL_BootCfgSetSRIOSERDESTxConfig(i, serdes_config_tx_value);
}
// Loop around till the SERDES PLL is not locked
uint32_t serdes_status = 0;
while (!(serdes_status & 0x1)) {
CSL_BootCfgGetSRIOSERDESStatus(&serdes_status);
}
// clear the LSU pending interrupts
CSL_SRIO_ClearLSUPendingInterrupt(srio_handle, 0xFFFFFFFF, 0xFFFFFFFF);
// set srio names ids etc
internal::ConfigSrioIds(srio_handle, config);
// set different srio flag features
internal::ConfigSrioFeatures(srio_handle, config);

// Configure the component tag CSR, is not used, needed when no DeviceId
CSL_SRIO_SetCompTagCSR(srio_handle, 0x00000000);

// Configure the PLM for all the ports.
//TODO Дебаг 2015 useIdle1
SRIO_PLM_IMPL_CONTROL implControl;
for (int i = 0; i < kSrioPortCount; i++) {
// Set the PLM Port Silence Timer.
CSL_SRIO_SetPLMPortSilenceTimer(srio_handle, i, 0x2);
/* TODO: We need to ensure that the Port 0 is configured to support both
* the 2x and 4x modes. The Port Width field is read only. So here we simply
* ensure that the Input and Output ports are enabled. */
CSL_SRIO_EnableInputPort(srio_handle, i);
CSL_SRIO_EnableOutputPort(srio_handle, i);
// Set the PLM Port Discovery Timer.
CSL_SRIO_SetPLMPortDiscoveryTimer(srio_handle, i, 0x2);
// Reset the Port Write Reception capture
CSL_SRIO_SetPortWriteReceptionCapture(srio_handle, i, 0x0);

// Get the PLM Implementation specific control
CSL_SRIO_GetPortPLMImplSpecificControl(srio_handle, i, &implControl);
implControl.useIdle1 = 1;
CSL_SRIO_SetPLMPortImplSpecificControl(srio_handle, i, &implControl);
}
// Set the Port link timeout CSR
CSL_SRIO_SetPortLinkTimeoutCSR(srio_handle, 0x000FFF);
// Set the Port General CSR: Only executing as Master Enable
CSL_SRIO_SetPortGeneralCSR(srio_handle, 0, 1, 0);
// Clear the sticky register bits
CSL_SRIO_SetLLMResetControl(srio_handle, 1);
/* Set the device id to be 0 for the Maintenance Port-Write operation
* to report errors to a system host. */
CSL_SRIO_SetPortWriteDeviceId(srio_handle, 0x0, 0x0, 0x0);
// Set the Data Streaming MTU
CSL_SRIO_SetDataStreamingMTU(srio_handle, 64);
/* Configure the path mode for the ports. */
for (int i = 0; i < kSrioPortCount; i++) {
CSL_SRIO_SetPLMPortPathControlMode(srio_handle, i, config.path_mode);
}
// Set the LLM Port IP Prescalar
CSL_SRIO_SetLLMPortIPPrescalar(srio_handle, 0x21);
// Enable the peripheral
CSL_SRIO_EnablePeripheral(srio_handle);
// Configuration has been completed
CSL_SRIO_SetBootComplete(srio_handle, 1);
// Check that all ports were initialized
int checked_port_count = kSrioPortCount;
// in 4x mode only port 1 returns port ok
if (config.path_mode == kSrioMode1port4x) {
checked_port_count = 1;
}
for (int i = 0; i < checked_port_count; i++) {
int retries_count = 0;
for (retries_count = 0; retries_count < config.num_port_checks;
++retries_count) {
if (CSL_SRIO_IsPortOk(srio_handle, i) == TRUE) {
break;
}
}
if (retries_count == config.num_port_checks) {
Raise(kErrorSrioPortInit);
}
}

/* Set all the queues 0 to operate at the same priority level and to
* send packets onto Port 1 */
for (int i = 0 ; i < 16; i++) {
CSL_SRIO_SetTxQueueSchedInfo(srio_handle, i, 0, 0);
}

/* Set the Doorbell route to determine which routing table is to be used
* This configuration implies that the Interrupt Routing Table is configured as
* follows:-
* Interrupt Destination 0 - INTDST 16
* Interrupt Destination 1 - INTDST 17
* Interrupt Destination 2 - INTDST 18
* Interrupt Destination 3 - INTDST 19
*/
CSL_SRIO_SetDoorbellRoute(srio_handle, 1);

/* Route the Doorbell interrupts.
* Doorbell Register 0 - All 16 Doorbits are routed to Interrupt Destination 0.
* Doorbell Register 1 - All 16 Doorbits are routed to Interrupt Destination 1.
* Doorbell Register 2 - All 16 Doorbits are routed to Interrupt Destination 2.
* Doorbell Register 3 - All 16 Doorbits are routed to Interrupt Destination 3. */
for (int i = 0; i < 16; i++) {
CSL_SRIO_RouteDoorbellInterrupts(srio_handle, 0, i, 0);
CSL_SRIO_RouteDoorbellInterrupts(srio_handle, 1, i, 1);
CSL_SRIO_RouteDoorbellInterrupts(srio_handle, 2, i, 2);
CSL_SRIO_RouteDoorbellInterrupts(srio_handle, 3, i, 3);
}

// this causes some strange errors
// srio_handle->RIO_PLM[0].RIO_PLM_SP_LONG_CS_TX1 = 0x2003F044; }

Hi, Ganapathi!

Do you have any news for me?