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C6670 NAND Bootload Multicore

m t
Prodigy 110 points

Hi,

I have set my C6670 to bootload from NAND storage using IBL. This involved first setting IBL up via EEPROM and then flashing the image to NAND storage. I currently have a simple hello world image running.

I would like to bootload a single image on all 4 cores of my C6670. I have prepared an image, where based on the core number (i.e. DNUM), the value written to a variable is different. This way, I can tell that each core has loaded the image and is running it independently.

I was wondering if someone could walk me through what I would need to do to load this image on all 4 cores of my C6670 using this NAND-IBL setup. I came across the MAD utilities while searching, but it seemed too complicated for loading just a single image on all cores (rather than different images on each core). I have seen discussions around this, but haven't really encountered a working solution.

Thank you for your help!

  • 0
    TI__Guru* 81335 points

    Hi,

    You can use MAD utility to load different images on each core. Please walk through the demo from MAD utils user guide.

    Thank you.

  • 0 in reply to Raja
    Prodigy 110 points
    Thanks. I tried following the prelinker mode example, and had some issues building the MAD Loader. I got the following error:

    "lnk_C6670.cmd", line 73: error: program will not fit into available memory.
    placement with alignment fails for section ".const" size 0x708 . Available
    memory ranges:
    PMEM0 size: 0x7b4c unused: 0x250 max hole: 0x250

    I fixed this by incorporating the contents of this linker file with an existing linker file that works, and expanding the space allocated in DDR.

    I am now using the MAP tools to generate the output image for app1, app2 (provided in the examples, as well). Now I get the following error:
    ERROR: mal_app placement in filesystem invalidates its linked address. Please link mal_app assuming file placement at address 0x9E001038
    ERROR: nml placement in filesystem invalidates its linked address. Please link nml assuming file placement at address 0x9E00A038

    Has anyone else encountered this issue? I'm not sure how to proceed... And I'm getting these errors from simply building the provided sample code, so I don't know what else to reference to boot an image on all cores of my C6670.

    Thanks for your help.
  • 0
    TI__Guru** 115300 points

    MT,

    For your usecase, I wouldn`t recommend using the MAD utilities. Once your primary core has booted, all you need to do is populate the magic addresses for the secondary core and issue an IPC interrupt. This process of populating the magic address and then issue IPC interrupts to wake up scondary cores has been described in the srioboot_helloworld.c file in the SDK

    I have provided a snapshot of the code here for your reference:

    /* Unlock the chip registers */
DEVICE_REG32_W(KICK0, 0x83e70b13);
DEVICE_REG32_W(KICK1, 0x95a4f1e0);

/* Writing the entry address to other cores */
for (core = 1; core < pform_info.cpu.core_count; core++)
{
sprintf(boot_msg, "\r\n\r\nBooting Hello World image on Core %d from Core 0 ...", core);
write_uart(boot_msg);

DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);

/* Delay 1 sec */
platform_delay(1);
}
for (core = 1; core < pform_info.cpu.core_count; core++)
{
/* IPC interrupt other cores */
DEVICE_REG32_W(IPCGR(core), 1);
platform_delay(1000);
}


    Regards,
    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 110 points

    Hi Rahul,

    Thanks for your response.

    I ran into this example when reading another thread, before trying the MAD utilities. However, I couldn't get it to work...

    Do I just need to have this IPC interrupt code in my image? Once I compile the image to .out, can I load it with any bootloading mechanism? For instance, ROM Ethernet bootloader? Also, is there any special switch configuration I need to have, besides the standard for Ethernet bootloading?

    I have tested ROM Ethernet with a simple image, so I know that works correctly. So it must be an issue with my integration of the IPC interrupt code.

    Thanks!

  • 0 in reply to m t
    TI__Guru* 81335 points

    As Rahul mentioned above, you can integrate the above in hello world example to wake up the secondary cores.

    Please refer the docs on NAND boot examples to convert the image to boot.

    PATH: ~\ti\mcsdk_2_0x_0x_0x\tools\boot_loader\examples\i2c\nand

    Please refer below thread as well,

    Thank you.

  • 0 in reply to Raja
    Prodigy 110 points

    Hi,

    I still haven't been able to get it to work. I have decided to backtrack a bit and start with a simpler image to verify that I'm setting up the NAND boot correctly. I've listed the steps I'm taking in detail below. It would be extremely helpful if someone could let me know where I'm missing something.

    The simple.out image I reference below is a very simple image that simply sets a global variable x to 100. I have attached it to this message. I would first like to verify that this works before trying the multi-boot image.

    I check if x has been written to 100 by looking at the simple.map file generated by CCS to get the memory address of x (in my case 0x8000278c). After completing step 13 below, I check the value at this address in memory using the Memory Browser. However, I don't see 100.

    After I get this working, I hope to just replicate the procedure below with a new image that includes the segment of code Rahul shared above.

    Thanks for your help!

    ----------------------------------------------------

    1. Set boot mode dip switch to "No boot" mode.
    2. Copy i2crom_0x51_c6670_le.bin to tools/writer/eeprom/evmc6670l/bin.
    3. Edit eepromwrtier_input.txt so that file_name reads "i2crom_0x51_c6670_le.bin", bus_addr = 0x51, start_addr = 0, swap_data = 0.
    4. Open CCS, launch target configuration, and connect to core 0.
    5. Load eepromwriter_evm6770l.out to CCS, with GEL file evmc6670.gel configured. Make sure DDR is initialized.
    6. Use the memory browser to navigate to 0x0C000000. Right click, and select Load Memory. Load i2crom_0x51_c6670_le.bin as a Raw Data file. Select Run on the CCS toolbar to run the program. ** I saw "EEPROM programming completed successfully" in the console. **
    7. Generate desired image using CCS (e.g. simple.out).
    8. Convert to .bin using strip6x (e.g. strip6x -p -o simple.bin simple.out).
    9. Copy simple.bin to tools/writer/nand/evmc6670l/bin/.
    10. Edit nand_writer_input.txt so that file name reads simple.bin.
    11. Without power cycling the DSP, load nandwriter_evm6770l.out to core 0. Make sure DDR is initialized.
    12. Use the memory browser to navigate to 0x80000000. Right click, and select Load Memory. Load simple.bin as a Raw Data file. Select Run on the CCS toolbar to run the program. ** I saw "NAND programming completed successfully" in the console. **
    13. Finally, power cycle the DSP. Before turning it back on, change the dip switch settings to "IBL NAND boot on image 0" mode.

    0042.main.c 
    /*
 * main.c
 */

int x;

int main(void) {
    x = 100;
    return 0;
}