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66AK2E05 cannot read remote configuration register

Alok Singh14
Intellectual 350 points
Other Parts Discussed in Thread: 66AK2E05

Hi,

We are using 66AK2E05 processor as root complex and microsemi FPGA as an endpoint (PCIe 1). After setting the processor as rootcomplex we see DEBUG0 register shows that link is up but we cannot view endpoint configuration registers at 2102 0000 + offset 0x2000.

Where should we start with the debug? Link - up status should mean that we have link at the hardware layer and should be able to read remote configuration registers like vendor ID, device...

  • 0
    TI__Guru* 81335 points
    We are working on this and will get back to you shortly. Thank you for your patience.
  • 0
    TI__Guru** 116100 points

    I presume that you have configured the PCIe 1 correctly on your custom board as our example uses PCIe 0.
    Also you have modified the same for power domain for PCIe 1 and CSl APIs.
    CSL_PCIE_1, CSL_PSC_LPSC_PCIE_1

    Please make sure that Link is stable.

    Put while(1); after link is up in our example and try to read the PCIe1 config register.

    Let me try the same in our two K2E EVM boards and update you.

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 350 points

    Yes, as far as we know PCIe 1 is configured exactly as the example project. We have looked at the link at seems to be stable. Everytime we ping the DEBUG0 register from the uboot console link status always reads 0x11. Please let us know what you find with the eval board. We also tried an external device and connected to PCIe0, and got same result link is up and stable but cannot read config registers. Do we need to do anything special to read config registers. We try to manually read the config registers using "md" uboot command.

  • 0 in reply to Alok Singh14
    TI__Guru** 116100 points

    I have connected two K2E boards and running the PCIe example as EP on one EVM and RC as on other EVM.

    I have put "while(1);" after link up and reading the PCIe 0 config register and able to find the DSP's PCIe ID (0x104C)

    LOG:

    [C66xx_0] **********************************************
    *             PCIe Test Start                *
    *                EP mode                     *
    **********************************************

    Version #: 0x02010001; string PCIE LLD Revision: 02.01.00.01:Sep 30 2015:00:14:39

    Debug: Serdes Setup Successfully
    Power domain is already enabled.  You probably re-ran without device reset (which is OK)
    PCIe Power Up.
    PLL configured.
    Successfully configured Inbound Translation!
    Successfully configured Outbound Translation!
    Starting link training...
    **********************************************
    *             PCIe Test Start                *
    *                RC mode                     *
    **********************************************

    Version #: 0x02010001; string PCIE LLD Revision: 02.01.00.01:Sep 30 2015:00:14:39

    Debug: Serdes Setup Successfully
    Power domain is already enabled.  You probably re-ran without device reset (which is OK)
    PCIe Power Up.
    PLL configured.
    Successfully configured Inbound Translation!
    Successfully configured Outbound Translation!
    Starting link training...
    Link is up.
    Link is up.

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 350 points

    We are still unable to view PCIe ID for the FPGA with "while(1)" after link up. Can you please send me the snapshot of the PCIe0 config, SERDES config, CMD status and any other settings that may cause issue.

    Thanks,

  • 0 in reply to Alok Singh14
    Intellectual 350 points

    Update:.

    Every time we check DEBUG0 register it LTSSM state shows 0x11 which means  "link is up" . But when we checked FPGA (endpoint status) it  shows the link at 02 (polling active) and never changes. This makes me think DEBUG0 status is BOGUS as link is not up. What are other ways to check and properly link train ? Can you please send us the snapshot of the PCIe related register settings?

  • 0 in reply to Alok Singh14
    TI__Guru** 116100 points
    Dear Alok,
    Here is the register dump for PCIe0 from K2E boards.

    PCIe0 EP device:
    0x21801040 000035001 00000000 00000000 00000000 00807005
    00000000 00000000 00000000 00000000 00000000
    00000000 00000000 00020010 00008701 0000281F
    00035422 10220000 00000000 00000000 00000000
    00000000 0000001F 00000000 00000006 00000002

    PCIe0 RC device:
    0x21801040 00035001 00000000 00000000 00000000 00807005
    00000000 00000000 00000000 00000000 00000000
    00000000 00000000 00420010 00008001 0000281F
    00135422 30220008 00000040 004003C0 00000000
    00000000 0000001F 00000000 00000006 00010002

    PCIe0 EP device:
    0x21801000 8888104C 00100146 00000001 00000000 00000000
    70000000 00000008 00000008 00000008 00000008
    00000000 00010000 00000000 00000040 00000000

    PCIe0 RC device:
    0x21801000 8888104C 00100146 00000001 00010000 00000000
    90000000 00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000040 00000000


    PCIe0 EP device:
    0x21801700 00C00040 FFFFFFFF 07000004 1B0F6400 00030120 00000000
    000103AA 00000500 00000000 00000003 03763311 08000410
    0001702F 00017005 000FFFFF 00000000 0000000F 00000000



    PCIe0 RC device:
    0x21801700 00C00040 FFFFFFFF 07000004 1B0F6400 00030120 00000000
    000103AA 00000500 00000000 00000003 03AEDB11 08000410
    0001702F 00017005 000FFFFF 00000000 0000000F 00000000

    Also please make sure that FPGA PCIe EP device is enumerating or initializing (running) first as K2E PCIe device doesn't support hot plug.

    What I did is, firstly I will run the PCIe EP code on 1st K2E EVM board and secondly, I will run the PCIe RC code on other K2E EVM board.

    Please refer to the following TI FAQ wiki page.
    processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices
    processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices