This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Data passing between CPU and DSP

Hi,

I am using the TMDSEVM6678LE for the first time. In fact this is my first project using a board ever. I am a bit lost as to how to get my program running.

Here is where I am stuck: My program doesn't do the addition correctly, even though it is able to access the code properly. I mean the control is reaching every line in the main.c and vecSum.c files (see below)

I tried created an empty project with main.c to write a simple vector addition program using CCSv6.1. Following are the project properties and the files in the explorer.

                                     

This project builds fine. But my problem is that it gives the following warnings :

1) Can someone please explain what the warnings mean? I understand there are some sections in the .cmd file called MEMORY and SECTIONS. I am not clear even after reading up on this as to what it actually does.

2) I am able to connect the core0 and load the TrialProgs.out onto it and also get it running. But the vectors I have defined don't seem to be accessed. As in, I cant see The output Vector holding the sum. Is my program not able to access the correct memory? why is it not able to traverse the arrays defined or perform additions?

3) .cmd files define the memory map of the target device. Is that correct? Can i modify the .cmd file? or can I make my own .cmd file? can there be more than one .cmd files in the project in that case? 

4) how does one pass data from cpu memory to dsp memory? I seem to understand that using the ccxml and cmd the .out is created and when loaded on to the connected core it uses the memory map from the cmd file to access the target core's memory. is this correct? 

Also attaching my small code: 

/*
* ****main.c******
*/
#include<time.h>
#include<stdio.h>
#include "vecSum.h"


#define MAX_SIZE 10

int x[MAX_SIZE] = {1,2,3,4,5,6,7,8,9,10};
int y[MAX_SIZE] = {10,20,30,40,50,60,70,80,90,100};

int main(void) {

   clock_t overhead, start, run_time;
   int res[MAX_SIZE];

   start = clock();
   overhead = clock() - start;

   start = clock();
   vecSum(x,y,res, MAX_SIZE);
   run_time = clock() - start - overhead;

   printf("run time: %d", run_time);

   return 0;
}

/*
* vecSum.c
* */
#include "vecSum.h"

void vecSum(int *in1, int *in2, int *out, int size){
   int i;
   for (i = 0; i < size; i++) {
   out[i] = in1[i] + in2[i]; // I can see in watch window i= 0 to size-1 but in1[i] and in2[i] when i>0 isn't showing correctly in watch.Also additions are not happening
   }
}

Questions and the program is extremely naive, but working with a non trivial board for the first time is pretty overwhelming. Answer and corrections are eagerly awaited. 

Thanks in advance.

Regards,

py.

  • Can you please attach the C6678.cmd file ?
    It seems to be the problem us due to the linker command file.

    Able to build any C6678 based hello world program and able to run on any of the cores ?
  • Hi Titusrathinaraj Stalin,

    Thank you for the reply. Firstly I realized that i need to "watch expression"  to see whether correct values are being accessed. And I can see that the addition is happening correctly. I feel a bit stupid now and I apologize for incorrectly saying that the addition is not happening.

    BUT the rest of my questions about the warnings and cmd files remain. So below is the C6678.cmd file (appears in the drop down list of linker command files in project properties) 

    Few things I think i should mention :

    1) the cmd file is used as is and has not been modified.

    2) I have done Connect Target for only core 0. 

    The contents of the file are pasted below. 

    /****************************************************************************/

    /*  C6678.cmd                                                               */

    /*  Copyright (c) 2011 Texas Instruments Incorporated                       */

    /*  Author: Rafael de Souza                                                 */

    /*                                                                          */

    /*    Description: This file is a sample linker command file that can be    */

    /*                 used for linking programs built with the C compiler and  */

    /*                 running the resulting .out file on an C6678              */

    /*                 device.  Use it as a guideline.  You will want to        */

    /*                 change the memory layout to match your specific C6xxx    */

    /*                 target system.  You may want to change the allocation    */

    /*                 scheme according to the size of your program.            */

    /*                                                                          */

    /*    Usage:       The map below divides the external memory in segments    */

    /*                 Use the linker option --define=COREn=1                   */

    /*                 Where n is the core number.                              */

    /*                                                                          */

    /****************************************************************************/

    MEMORY

    {

        SHRAM:           o = 0x0C000000 l = 0x00400000   /* 4MB Multicore shared Memmory */

      

        CORE0_L2_SRAM:   o = 0x10800000 l = 0x00080000   /* 512kB CORE0 L2/SRAM */

        CORE0_L1P_SRAM:  o = 0x10E00000 l = 0x00008000   /* 32kB CORE0 L1P/SRAM */

        CORE0_L1D_SRAM:  o = 0x10F00000 l = 0x00008000   /* 32kB CORE0 L1D/SRAM */

      

        CORE1_L2_SRAM:   o = 0x11800000 l = 0x00080000   /* 512kB CORE1 L2/SRAM */

        CORE1_L1P_SRAM:  o = 0x11E00000 l = 0x00008000   /* 32kB CORE1 L1P/SRAM */

        CORE1_L1D_SRAM:  o = 0x11F00000 l = 0x00008000   /* 32kB CORE1 L1D/SRAM */

      

        CORE2_L2_SRAM:   o = 0x12800000 l = 0x00080000   /* 512kB CORE2 L2/SRAM */

        CORE2_L1P_SRAM:  o = 0x12E00000 l = 0x00008000   /* 32kB CORE2 L1P/SRAM */

        CORE2_L1D_SRAM:  o = 0x12F00000 l = 0x00008000   /* 32kB CORE2 L1D/SRAM */

      

        CORE3_L2_SRAM:   o = 0x13800000 l = 0x00080000   /* 512kB CORE3 L2/SRAM */

        CORE3_L1P_SRAM:  o = 0x13E00000 l = 0x00008000   /* 32kB CORE3 L1P/SRAM */

        CORE3_L1D_SRAM:  o = 0x13F00000 l = 0x00008000   /* 32kB CORE3 L1D/SRAM */

      

        CORE4_L2_SRAM:   o = 0x14800000 l = 0x00080000   /* 512kB CORE4 L2/SRAM */

        CORE4_L1P_SRAM:  o = 0x14E00000 l = 0x00008000   /* 32kB CORE4 L1P/SRAM */

        CORE4_L1D_SRAM:  o = 0x14F00000 l = 0x00008000   /* 32kB CORE4 L1D/SRAM */

      

        CORE5_L2_SRAM:   o = 0x15800000 l = 0x00080000   /* 512kB CORE5 L2/SRAM */

        CORE5_L1P_SRAM:  o = 0x15E00000 l = 0x00008000   /* 32kB CORE5 L1P/SRAM */

        CORE5_L1D_SRAM:  o = 0x15F00000 l = 0x00008000   /* 32kB CORE5 L1D/SRAM */

        

        CORE6_L2_SRAM:   o = 0x16800000 l = 0x00080000   /* 512kB CORE6 L2/SRAM */

        CORE6_L1P_SRAM:  o = 0x16E00000 l = 0x00008000   /* 32kB CORE6 L1P/SRAM */

        CORE6_L1D_SRAM:  o = 0x16F00000 l = 0x00008000   /* 32kB CORE6 L1D/SRAM */

      

        CORE7_L2_SRAM:   o = 0x17800000 l = 0x00080000   /* 512kB CORE7 L2/SRAM */

        CORE7_L1P_SRAM:  o = 0x17E00000 l = 0x00008000   /* 32kB CORE7 L1P/SRAM */

        CORE7_L1D_SRAM:  o = 0x17F00000 l = 0x00008000   /* 32kB CORE7 L1D/SRAM */

      

        EMIF16_CS2:      o = 0x70000000 l = 0x04000000   /* 64MB EMIF16 CS2 Data Memory */

        EMIF16_CS3:      o = 0x74000000 l = 0x04000000   /* 64MB EMIF16 CS3 Data Memory */

        EMIF16_CS4:      o = 0x78000000 l = 0x04000000   /* 64MB EMIF16 CS4 Data Memory */

        EMIF16_CS5:      o = 0x7C000000 l = 0x04000000   /* 64MB EMIF16 CS5 Data Memory */

      

        CORE0_DDR3:      o = 0x80000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

        CORE1_DDR3:      o = 0x90000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE1 */  

        CORE2_DDR3:      o = 0xA0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE2 */  

        CORE3_DDR3:      o = 0xB0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE3 */  

        CORE4_DDR3:      o = 0xC0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE4 */  

        CORE5_DDR3:      o = 0xD0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE5 */  

        CORE6_DDR3:      o = 0xE0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE6 */  

        CORE7_DDR3:      o = 0xF0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE7 */  

    }

     

    SECTIONS

    {

    #ifdef CORE0

        .text          >  CORE0_L2_SRAM

        .stack         >  CORE0_L2_SRAM

        .bss           >  CORE0_L2_SRAM

        .cio           >  CORE0_L2_SRAM

        .const         >  CORE0_L2_SRAM

        .data          >  CORE0_L2_SRAM

        .switch        >  CORE0_L2_SRAM

        .sysmem        >  CORE0_L2_SRAM

        .far           >  CORE0_L2_SRAM

        .args          >  CORE0_L2_SRAM

        .ppinfo        >  CORE0_L2_SRAM

        .ppdata        >  CORE0_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE0_L2_SRAM

        .cinit         >  CORE0_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE0_L2_SRAM

        .init_array    >  CORE0_L2_SRAM

        .neardata      >  CORE0_L2_SRAM

        .fardata       >  CORE0_L2_SRAM

        .rodata        >  CORE0_L2_SRAM

        .c6xabi.exidx  >  CORE0_L2_SRAM

        .c6xabi.extab  >  CORE0_L2_SRAM

    #endif

    #ifdef CORE1

        .text          >  CORE1_L2_SRAM

        .stack         >  CORE1_L2_SRAM

        .bss           >  CORE1_L2_SRAM

        .cio           >  CORE1_L2_SRAM

        .const         >  CORE1_L2_SRAM

        .data          >  CORE1_L2_SRAM

        .switch        >  CORE1_L2_SRAM

        .sysmem        >  CORE1_L2_SRAM

        .far           >  CORE1_L2_SRAM

        .args          >  CORE1_L2_SRAM

        .ppinfo        >  CORE1_L2_SRAM

        .ppdata        >  CORE1_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE1_L2_SRAM

        .cinit         >  CORE1_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE1_L2_SRAM

        .init_array    >  CORE1_L2_SRAM

        .neardata      >  CORE1_L2_SRAM

        .fardata       >  CORE1_L2_SRAM

        .rodata        >  CORE1_L2_SRAM

        .c6xabi.exidx  >  CORE1_L2_SRAM

        .c6xabi.extab  >  CORE1_L2_SRAM

    #endif

    #ifdef CORE2

        .text          >  CORE2_L2_SRAM

        .stack         >  CORE2_L2_SRAM

        .bss           >  CORE2_L2_SRAM

        .cio           >  CORE2_L2_SRAM

        .const         >  CORE2_L2_SRAM

        .data          >  CORE2_L2_SRAM

        .switch        >  CORE2_L2_SRAM

        .sysmem        >  CORE2_L2_SRAM

        .far           >  CORE2_L2_SRAM

        .args          >  CORE2_L2_SRAM

        .ppinfo        >  CORE2_L2_SRAM

        .ppdata        >  CORE2_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE2_L2_SRAM

        .cinit         >  CORE2_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE2_L2_SRAM

        .init_array    >  CORE2_L2_SRAM

        .neardata      >  CORE2_L2_SRAM

        .fardata       >  CORE2_L2_SRAM

        .rodata        >  CORE2_L2_SRAM

        .c6xabi.exidx  >  CORE2_L2_SRAM

        .c6xabi.extab  >  CORE2_L2_SRAM

    #endif

    #ifdef CORE3

        .text          >  CORE3_L2_SRAM

        .stack         >  CORE3_L2_SRAM

        .bss           >  CORE3_L2_SRAM

        .cio           >  CORE3_L2_SRAM

        .const         >  CORE3_L2_SRAM

        .data          >  CORE3_L2_SRAM

        .switch        >  CORE3_L2_SRAM

        .sysmem        >  CORE3_L2_SRAM

        .far           >  CORE3_L2_SRAM

        .args          >  CORE3_L2_SRAM

        .ppinfo        >  CORE3_L2_SRAM

        .ppdata        >  CORE3_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE3_L2_SRAM

        .cinit         >  CORE3_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE3_L2_SRAM

        .init_array    >  CORE3_L2_SRAM

        .neardata      >  CORE3_L2_SRAM

        .fardata       >  CORE3_L2_SRAM

        .rodata        >  CORE3_L2_SRAM

        .c6xabi.exidx  >  CORE3_L2_SRAM

        .c6xabi.extab  >  CORE3_L2_SRAM

    #endif

    #ifdef CORE4

        .text          >  CORE4_L2_SRAM

        .stack         >  CORE4_L2_SRAM

        .bss           >  CORE4_L2_SRAM

        .cio           >  CORE4_L2_SRAM

        .const         >  CORE4_L2_SRAM

        .data          >  CORE4_L2_SRAM

        .switch        >  CORE4_L2_SRAM

        .sysmem        >  CORE4_L2_SRAM

        .far           >  CORE4_L2_SRAM

        .args          >  CORE4_L2_SRAM

        .ppinfo        >  CORE4_L2_SRAM

        .ppdata        >  CORE4_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE4_L2_SRAM

        .cinit         >  CORE4_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE4_L2_SRAM

        .init_array    >  CORE4_L2_SRAM

        .neardata      >  CORE4_L2_SRAM

        .fardata       >  CORE4_L2_SRAM

        .rodata        >  CORE4_L2_SRAM

        .c6xabi.exidx  >  CORE4_L2_SRAM

        .c6xabi.extab  >  CORE4_L2_SRAM

    #endif

    #ifdef CORE5

        .text          >  CORE5_L2_SRAM

        .stack         >  CORE5_L2_SRAM

        .bss           >  CORE5_L2_SRAM

        .cio           >  CORE5_L2_SRAM

        .const         >  CORE5_L2_SRAM

        .data          >  CORE5_L2_SRAM

        .switch        >  CORE5_L2_SRAM

        .sysmem        >  CORE5_L2_SRAM

        .far           >  CORE5_L2_SRAM

        .args          >  CORE5_L2_SRAM

        .ppinfo        >  CORE5_L2_SRAM

        .ppdata        >  CORE5_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE5_L2_SRAM

        .cinit         >  CORE5_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE5_L2_SRAM

        .init_array    >  CORE5_L2_SRAM

        .neardata      >  CORE5_L2_SRAM

        .fardata       >  CORE5_L2_SRAM

        .rodata        >  CORE5_L2_SRAM

        .c6xabi.exidx  >  CORE5_L2_SRAM

        .c6xabi.extab  >  CORE5_L2_SRAM

    #endif

    #ifdef CORE6

        .text          >  CORE6_L2_SRAM

        .stack         >  CORE6_L2_SRAM

        .bss           >  CORE6_L2_SRAM

        .cio           >  CORE6_L2_SRAM

        .const         >  CORE6_L2_SRAM

        .data          >  CORE6_L2_SRAM

        .switch        >  CORE6_L2_SRAM

        .sysmem        >  CORE6_L2_SRAM

        .far           >  CORE6_L2_SRAM

        .args          >  CORE6_L2_SRAM

        .ppinfo        >  CORE6_L2_SRAM

        .ppdata        >  CORE6_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE6_L2_SRAM

        .cinit         >  CORE6_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE6_L2_SRAM

        .init_array    >  CORE6_L2_SRAM

        .neardata      >  CORE6_L2_SRAM

        .fardata       >  CORE6_L2_SRAM

        .rodata        >  CORE6_L2_SRAM

        .c6xabi.exidx  >  CORE6_L2_SRAM

        .c6xabi.extab  >  CORE6_L2_SRAM

    #endif

    #ifdef CORE7

        .text          >  CORE7_L2_SRAM

        .stack         >  CORE7_L2_SRAM

        .bss           >  CORE7_L2_SRAM

        .cio           >  CORE7_L2_SRAM

        .const         >  CORE7_L2_SRAM

        .data          >  CORE7_L2_SRAM

        .switch        >  CORE7_L2_SRAM

        .sysmem        >  CORE7_L2_SRAM

        .far           >  CORE7_L2_SRAM

        .args          >  CORE7_L2_SRAM

        .ppinfo        >  CORE7_L2_SRAM

        .ppdata        >  CORE7_L2_SRAM

      

        /* COFF sections */

        .pinit         >  CORE7_L2_SRAM

        .cinit         >  CORE7_L2_SRAM

      

        /* EABI sections */

        .binit         >  CORE7_L2_SRAM

        .init_array    >  CORE7_L2_SRAM

        .neardata      >  CORE7_L2_SRAM

        .fardata       >  CORE7_L2_SRAM

        .rodata        >  CORE7_L2_SRAM

        .c6xabi.exidx  >  CORE7_L2_SRAM

        .c6xabi.extab  >  CORE7_L2_SRAM

    #endif

    }

    Thank you once again.. Awaiting your answers to the other questions.

    Regards,

    Py.

    /****************************************************************************//*  C6678.cmd                                                               *//*  Copyright (c) 2011 Texas Instruments Incorporated                       *//*  Author: Rafael de Souza                                                 *//*                                                                          *//*    Description: This file is a sample linker command file that can be    *//*                 used for linking programs built with the C compiler and  *//*                 running the resulting .out file on an C6678              *//*                 device.  Use it as a guideline.  You will want to        *//*                 change the memory layout to match your specific C6xxx    *//*                 target system.  You may want to change the allocation    *//*                 scheme according to the size of your program.            *//*                                                                          *//*    Usage:       The map below divides the external memory in segments    *//*                 Use the linker option --define=COREn=1                   *//*                 Where n is the core number.                              *//*                                                                          *//****************************************************************************/
    MEMORY{    SHRAM:           o = 0x0C000000 l = 0x00400000   /* 4MB Multicore shared Memmory */      CORE0_L2_SRAM:   o = 0x10800000 l = 0x00080000   /* 512kB CORE0 L2/SRAM */    CORE0_L1P_SRAM:  o = 0x10E00000 l = 0x00008000   /* 32kB CORE0 L1P/SRAM */    CORE0_L1D_SRAM:  o = 0x10F00000 l = 0x00008000   /* 32kB CORE0 L1D/SRAM */      CORE1_L2_SRAM:   o = 0x11800000 l = 0x00080000   /* 512kB CORE1 L2/SRAM */    CORE1_L1P_SRAM:  o = 0x11E00000 l = 0x00008000   /* 32kB CORE1 L1P/SRAM */    CORE1_L1D_SRAM:  o = 0x11F00000 l = 0x00008000   /* 32kB CORE1 L1D/SRAM */      CORE2_L2_SRAM:   o = 0x12800000 l = 0x00080000   /* 512kB CORE2 L2/SRAM */    CORE2_L1P_SRAM:  o = 0x12E00000 l = 0x00008000   /* 32kB CORE2 L1P/SRAM */    CORE2_L1D_SRAM:  o = 0x12F00000 l = 0x00008000   /* 32kB CORE2 L1D/SRAM */      CORE3_L2_SRAM:   o = 0x13800000 l = 0x00080000   /* 512kB CORE3 L2/SRAM */    CORE3_L1P_SRAM:  o = 0x13E00000 l = 0x00008000   /* 32kB CORE3 L1P/SRAM */    CORE3_L1D_SRAM:  o = 0x13F00000 l = 0x00008000   /* 32kB CORE3 L1D/SRAM */      CORE4_L2_SRAM:   o = 0x14800000 l = 0x00080000   /* 512kB CORE4 L2/SRAM */    CORE4_L1P_SRAM:  o = 0x14E00000 l = 0x00008000   /* 32kB CORE4 L1P/SRAM */    CORE4_L1D_SRAM:  o = 0x14F00000 l = 0x00008000   /* 32kB CORE4 L1D/SRAM */      CORE5_L2_SRAM:   o = 0x15800000 l = 0x00080000   /* 512kB CORE5 L2/SRAM */    CORE5_L1P_SRAM:  o = 0x15E00000 l = 0x00008000   /* 32kB CORE5 L1P/SRAM */    CORE5_L1D_SRAM:  o = 0x15F00000 l = 0x00008000   /* 32kB CORE5 L1D/SRAM */        CORE6_L2_SRAM:   o = 0x16800000 l = 0x00080000   /* 512kB CORE6 L2/SRAM */    CORE6_L1P_SRAM:  o = 0x16E00000 l = 0x00008000   /* 32kB CORE6 L1P/SRAM */    CORE6_L1D_SRAM:  o = 0x16F00000 l = 0x00008000   /* 32kB CORE6 L1D/SRAM */      CORE7_L2_SRAM:   o = 0x17800000 l = 0x00080000   /* 512kB CORE7 L2/SRAM */    CORE7_L1P_SRAM:  o = 0x17E00000 l = 0x00008000   /* 32kB CORE7 L1P/SRAM */    CORE7_L1D_SRAM:  o = 0x17F00000 l = 0x00008000   /* 32kB CORE7 L1D/SRAM */      EMIF16_CS2:      o = 0x70000000 l = 0x04000000   /* 64MB EMIF16 CS2 Data Memory */    EMIF16_CS3:      o = 0x74000000 l = 0x04000000   /* 64MB EMIF16 CS3 Data Memory */    EMIF16_CS4:      o = 0x78000000 l = 0x04000000   /* 64MB EMIF16 CS4 Data Memory */    EMIF16_CS5:      o = 0x7C000000 l = 0x04000000   /* 64MB EMIF16 CS5 Data Memory */      CORE0_DDR3:      o = 0x80000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */    CORE1_DDR3:      o = 0x90000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE1 */      CORE2_DDR3:      o = 0xA0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE2 */      CORE3_DDR3:      o = 0xB0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE3 */      CORE4_DDR3:      o = 0xC0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE4 */      CORE5_DDR3:      o = 0xD0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE5 */      CORE6_DDR3:      o = 0xE0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE6 */      CORE7_DDR3:      o = 0xF0000000 l = 0x10000000   /* 256MB DDR3 SDRAM for CORE7 */  } SECTIONS{#ifdef CORE0    .text          >  CORE0_L2_SRAM    .stack         >  CORE0_L2_SRAM    .bss           >  CORE0_L2_SRAM    .cio           >  CORE0_L2_SRAM    .const         >  CORE0_L2_SRAM    .data          >  CORE0_L2_SRAM    .switch        >  CORE0_L2_SRAM    .sysmem        >  CORE0_L2_SRAM    .far           >  CORE0_L2_SRAM    .args          >  CORE0_L2_SRAM    .ppinfo        >  CORE0_L2_SRAM    .ppdata        >  CORE0_L2_SRAM      /* COFF sections */    .pinit         >  CORE0_L2_SRAM    .cinit         >  CORE0_L2_SRAM      /* EABI sections */    .binit         >  CORE0_L2_SRAM    .init_array    >  CORE0_L2_SRAM    .neardata      >  CORE0_L2_SRAM    .fardata       >  CORE0_L2_SRAM    .rodata        >  CORE0_L2_SRAM    .c6xabi.exidx  >  CORE0_L2_SRAM    .c6xabi.extab  >  CORE0_L2_SRAM#endif
    #ifdef CORE1    .text          >  CORE1_L2_SRAM    .stack         >  CORE1_L2_SRAM    .bss           >  CORE1_L2_SRAM    .cio           >  CORE1_L2_SRAM    .const         >  CORE1_L2_SRAM    .data          >  CORE1_L2_SRAM    .switch        >  CORE1_L2_SRAM    .sysmem        >  CORE1_L2_SRAM    .far           >  CORE1_L2_SRAM    .args          >  CORE1_L2_SRAM    .ppinfo        >  CORE1_L2_SRAM    .ppdata        >  CORE1_L2_SRAM      /* COFF sections */    .pinit         >  CORE1_L2_SRAM    .cinit         >  CORE1_L2_SRAM      /* EABI sections */    .binit         >  CORE1_L2_SRAM    .init_array    >  CORE1_L2_SRAM    .neardata      >  CORE1_L2_SRAM    .fardata       >  CORE1_L2_SRAM    .rodata        >  CORE1_L2_SRAM    .c6xabi.exidx  >  CORE1_L2_SRAM    .c6xabi.extab  >  CORE1_L2_SRAM#endif
    #ifdef CORE2    .text          >  CORE2_L2_SRAM    .stack         >  CORE2_L2_SRAM    .bss           >  CORE2_L2_SRAM    .cio           >  CORE2_L2_SRAM    .const         >  CORE2_L2_SRAM    .data          >  CORE2_L2_SRAM    .switch        >  CORE2_L2_SRAM    .sysmem        >  CORE2_L2_SRAM    .far           >  CORE2_L2_SRAM    .args          >  CORE2_L2_SRAM    .ppinfo        >  CORE2_L2_SRAM    .ppdata        >  CORE2_L2_SRAM      /* COFF sections */    .pinit         >  CORE2_L2_SRAM    .cinit         >  CORE2_L2_SRAM      /* EABI sections */    .binit         >  CORE2_L2_SRAM    .init_array    >  CORE2_L2_SRAM    .neardata      >  CORE2_L2_SRAM    .fardata       >  CORE2_L2_SRAM    .rodata        >  CORE2_L2_SRAM    .c6xabi.exidx  >  CORE2_L2_SRAM    .c6xabi.extab  >  CORE2_L2_SRAM#endif
    #ifdef CORE3    .text          >  CORE3_L2_SRAM    .stack         >  CORE3_L2_SRAM    .bss           >  CORE3_L2_SRAM    .cio           >  CORE3_L2_SRAM    .const         >  CORE3_L2_SRAM    .data          >  CORE3_L2_SRAM    .switch        >  CORE3_L2_SRAM    .sysmem        >  CORE3_L2_SRAM    .far           >  CORE3_L2_SRAM    .args          >  CORE3_L2_SRAM    .ppinfo        >  CORE3_L2_SRAM    .ppdata        >  CORE3_L2_SRAM      /* COFF sections */    .pinit         >  CORE3_L2_SRAM    .cinit         >  CORE3_L2_SRAM      /* EABI sections */    .binit         >  CORE3_L2_SRAM    .init_array    >  CORE3_L2_SRAM    .neardata      >  CORE3_L2_SRAM    .fardata       >  CORE3_L2_SRAM    .rodata        >  CORE3_L2_SRAM    .c6xabi.exidx  >  CORE3_L2_SRAM    .c6xabi.extab  >  CORE3_L2_SRAM#endif
    #ifdef CORE4    .text          >  CORE4_L2_SRAM    .stack         >  CORE4_L2_SRAM    .bss           >  CORE4_L2_SRAM    .cio           >  CORE4_L2_SRAM    .const         >  CORE4_L2_SRAM    .data          >  CORE4_L2_SRAM    .switch        >  CORE4_L2_SRAM    .sysmem        >  CORE4_L2_SRAM    .far           >  CORE4_L2_SRAM    .args          >  CORE4_L2_SRAM    .ppinfo        >  CORE4_L2_SRAM    .ppdata        >  CORE4_L2_SRAM      /* COFF sections */    .pinit         >  CORE4_L2_SRAM    .cinit         >  CORE4_L2_SRAM      /* EABI sections */    .binit         >  CORE4_L2_SRAM    .init_array    >  CORE4_L2_SRAM    .neardata      >  CORE4_L2_SRAM    .fardata       >  CORE4_L2_SRAM    .rodata        >  CORE4_L2_SRAM    .c6xabi.exidx  >  CORE4_L2_SRAM    .c6xabi.extab  >  CORE4_L2_SRAM#endif
    #ifdef CORE5    .text          >  CORE5_L2_SRAM    .stack         >  CORE5_L2_SRAM    .bss           >  CORE5_L2_SRAM    .cio           >  CORE5_L2_SRAM    .const         >  CORE5_L2_SRAM    .data          >  CORE5_L2_SRAM    .switch        >  CORE5_L2_SRAM    .sysmem        >  CORE5_L2_SRAM    .far           >  CORE5_L2_SRAM    .args          >  CORE5_L2_SRAM    .ppinfo        >  CORE5_L2_SRAM    .ppdata        >  CORE5_L2_SRAM      /* COFF sections */    .pinit         >  CORE5_L2_SRAM    .cinit         >  CORE5_L2_SRAM      /* EABI sections */    .binit         >  CORE5_L2_SRAM    .init_array    >  CORE5_L2_SRAM    .neardata      >  CORE5_L2_SRAM    .fardata       >  CORE5_L2_SRAM    .rodata        >  CORE5_L2_SRAM    .c6xabi.exidx  >  CORE5_L2_SRAM    .c6xabi.extab  >  CORE5_L2_SRAM#endif
    #ifdef CORE6    .text          >  CORE6_L2_SRAM    .stack         >  CORE6_L2_SRAM    .bss           >  CORE6_L2_SRAM    .cio           >  CORE6_L2_SRAM    .const         >  CORE6_L2_SRAM    .data          >  CORE6_L2_SRAM    .switch        >  CORE6_L2_SRAM    .sysmem        >  CORE6_L2_SRAM    .far           >  CORE6_L2_SRAM    .args          >  CORE6_L2_SRAM    .ppinfo        >  CORE6_L2_SRAM    .ppdata        >  CORE6_L2_SRAM      /* COFF sections */    .pinit         >  CORE6_L2_SRAM    .cinit         >  CORE6_L2_SRAM      /* EABI sections */    .binit         >  CORE6_L2_SRAM    .init_array    >  CORE6_L2_SRAM    .neardata      >  CORE6_L2_SRAM    .fardata       >  CORE6_L2_SRAM    .rodata        >  CORE6_L2_SRAM    .c6xabi.exidx  >  CORE6_L2_SRAM    .c6xabi.extab  >  CORE6_L2_SRAM#endif
    #ifdef CORE7    .text          >  CORE7_L2_SRAM    .stack         >  CORE7_L2_SRAM    .bss           >  CORE7_L2_SRAM    .cio           >  CORE7_L2_SRAM    .const         >  CORE7_L2_SRAM    .data          >  CORE7_L2_SRAM    .switch        >  CORE7_L2_SRAM    .sysmem        >  CORE7_L2_SRAM    .far           >  CORE7_L2_SRAM    .args          >  CORE7_L2_SRAM    .ppinfo        >  CORE7_L2_SRAM    .ppdata        >  CORE7_L2_SRAM      /* COFF sections */    .pinit         >  CORE7_L2_SRAM    .cinit         >  CORE7_L2_SRAM      /* EABI sections */    .binit         >  CORE7_L2_SRAM    .init_array    >  CORE7_L2_SRAM    .neardata      >  CORE7_L2_SRAM    .fardata       >  CORE7_L2_SRAM    .rodata        >  CORE7_L2_SRAM    .c6xabi.exidx  >  CORE7_L2_SRAM    .c6xabi.extab  >  CORE7_L2_SRAM#endif}

  • Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.

  • Can you please attach your complete project ?
    I can try to build your code without any harmful warnings.
  • Hi Titusrathinaraj Stalin,

    Project is attached. 

    .TrialProgs.zip

  • Thank you Raja!
  • I'm able to build without any warning using the following linker command code.

    -c

    -heap  0x2000

    -stack 0x2000

    /* Memory Map  - the default */

    MEMORY

    {

           SHRAM:          o = 0x0C000000  l = 0x00400000   /* 4MB Multicore shared Memmory */

           L1D:     o = 00f00000h   l = 00007FFFh

           L1P:     o = 00e00000h   l = 00007FFFh

           L2:       o = 00800000h   l = 0007FFFFh

           DDR3:     o = 0x80000000  l = 0x10000000   /* 256MB DDR3 SDRAM */

    }

    SECTIONS

    {

       .csl_vect   >       L2

       .text       >       L2

       .stack      >       L2

       .bss        >       L2

       .cinit      >       L2

       .cio        >       L2

       .const      >       L2

       .data       >       L2

       .switch     >       L2

       .sysmem     >       L2

       .far        >       L2

       .testMem    >       L2

       .fardata > L2

       .neardata   > L2

       .rodata     > L2

    }

    6708.TrialProgs.zip

  • Hi,

    Thanks for your reply.

    I see that you have modified the .cmd file. It would be great if you could elaborate a little on what you did. Specifically the following questions:

    1)What was wrong with my file?
    2)Can you please explain what the warnings meant?
    3)So you removed the "CoreN " prefix to the MEMORY and SECTIONS. does that mean that this is a common map for all cores? I mean L1D 0= 0x00F00000 is called Local L1D SRAM in C6678 data sheet(sec. 2.3 : memory Map summary). "local" to what?
    4) I am able to run the project you gave me on multiple cores. I am confused as to how this is happening.
    5) Also the timing printf statement shows runtime as 0 ? how do i measure running times? what am I doing wrong?

    Thanks in advance.

    Cordially,
    py
  • Waiting for your reply!

    I see that you have modified the .cmd file. It would be great if you could elaborate a little on what you did. Specifically the following questions:

    1)What was wrong with my file?
    2)Can you please explain what the warnings meant?
    3)So you removed the "CoreN " prefix to the MEMORY and SECTIONS. does that mean that this is a common map for all cores? I mean L1D 0= 0x00F00000 is called Local L1D SRAM in C6678 data sheet(sec. 2.3 : memory Map summary). "local" to what?
    4) I am able to run the project you gave me on multiple cores. I am confused as to how this is happening. Your file seems similar to the C6678_unified.cmd
    5) Also the timing printf statement shows runtime as 0 ? how do i measure running times? what am I doing wrong?

    Thanks in advance.

    Cordially,
    py