tms320c6657: EDMA3TC ERRDET Read Error

Bradley Baker1

Part Number: TMS320C6657

What would cause a EDMA3TC read error when the source address is the McBSP1 FIFO data address?

I am attempting to set up the EDMA controller to read the McBSP1 Data FIFO but am getting a EDMA3TC ERRDET STAT field error of "0x00002601".

McBSP1 is set up with the FIFO enabled, and with RNUMEVT set to 32 words (32-bit).

The EDMA CC receives the event and transfers to TC0.

The first PaRAM set configuration is shown below. I have also included the TC register contents.

paramSet.OPT = 0;
paramSet.OPT = /* 0x........ */
(0x0 << 31 | /* PRIV = 0 R */
0x0 << 24 | /* PRIVID = 0 R */
0x0 << 23 | /* ITCCHE = 0 R/W Intermediate transfer chaining is disabled */
0x0 << 22 | /* TCCHE = 0 R/W Transfer complete chaining is disabled */
0x0 << 21 | /* ITCINTE = 0 R/W Intermediate transfer complete Int is disabled */
0x1 << 20 | /* TCINTE = 1 R/W Transfer complete interrupt is enabled */
0x26 << 12 | /* TCC = 38 R/W Transfer complete code = MCBSP1_REVT = 38 */
0x0 << 11 | /* TCCMODE = 0 Normal completion */
0x2 << 8 | /* FWID = 2 FIFO width 32-bit */
0x0 << 3 | /* STATIC = 0 R/W The param set will be modified after completion */
0x0 << 2 | /* SYNCDIM = 0 R/W A-synchronized transfer */
0x0 << 1 | /* DAM = 0 R/W Destination address increments */
0x0 << 0); /* SAM = 0 R/W Source address increments */

paramSet.SRC = MCBSP1_FIFO_DATA_ADDR; /* 0x22400000u */
paramSet.DST = (uint32_t)ddcPing;
paramSet.LINK = (uint16_t) (MCBSP1_RX_PONG_PARAMSET * SIZE_PARAMSET);
paramSet.ACNT = 8*4; /* 8 words (32-bit) */
paramSet.BCNT = 4; /* 32 words (32-bit) */
paramSet.CCNT = 1; /* not used */
paramSet.BCNTRLD = 0; /* BCNT reload upon CCNT zeroing (not used) */
paramSet.SRCBIDX = 0; /* FIFO - src addr does not incr upon ACNT zeroing */
paramSet.DSTBIDX = 8*4; /* dest addr incr by 32 */
paramSet.SRCCIDX = 0; /* not used */
paramSet.DSTCIDX = 0; /* not used */

EDMA_setPaRAM(EDMA3CC_BASE_ADDR, EDMA_MCBSP1_REVT, &paramSet);

over 7 years ago

0 Cvetolin Shulev-XID over 7 years ago

TI__Guru 65405 points

Hi Bradley,

I've forwarded this to the McBSP and EDMA experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 David Zaucha over 7 years ago in reply to Cvetolin Shulev-XID

TI__Expert 7570 points

Hi Bradley

If you are using the Processor SDK RTOS, www.ti.com/.../processor-sdk-c665x , there is a simple McBSP example which uses EDMA and illustrates the use of the McBSP Driver that may help.

David

0 Bradley Baker1 over 7 years ago in reply to David Zaucha

Prodigy 140 points

This a DO-178B safety critical application. For verification reasons we have elected not to use the TI-RTOS nor CSL. The CSL code has certainly been useful in many cases in trying to write drivers for the processor API. However, the useful examples seem to use the TI-RTOS. Even by using Understand on the code it doesn't take long for things to get so abstracted that it becomes difficult to determine what is going on at a register level.

Regardless, I stumbled across the answer during a forum search. This stumble rang a bell because I had run into the same roadblock when writing an API for a c6748 a few years ago. If the EDMA, and I suspect certain other peripherals, needs to access a memory address located in L2, such as a PaRAM destination address, it must do so using the CorePac0 L2 SRAM located at 0x10800000 (or CorePac1 L2 SRAM correspondingly). So something like (for the c6657 core 0):

paramSet.DST = ((uint32_t)&ddcEdmaPing[0]) | 0x10000000;

In the case of the 6748 the only documentation I found for this was the memory map in SPRS590E, Table 2-4. It has greyed out columns identifying which devices (DSP, EDMA, PRUSS, Master Periph, LCDC), do not have access to a particular memory range. Only the DSP has access to memory locations below 0x01C0 0000 for example.

The c6657 has no such indication in the memory map (SPRS814C, table 6-63). Where is it documented? In my haste must have missed it!

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tms320c6657: EDMA3TC ERRDET Read Error