Part Number: XEVMK2LX
we would like to use the JESD 204b interface on our EVM to read data from an external FPGA. The data will be 8b/10b encoded with a custom made protocol, and we would like to bypass the DFE to read the data. Is that possible with RTOS?
If it is not possible, is there a way to use other IOs like SGMII or PCIe without using the protocol? We tried the GPIOs, but they are to slow for our purposes.
In general, after studying the examples that come with the latest processor SDK, I have the impression that they are all very complex. Is there a minimal example for SGMII, PCIe and JESD204b
Please click the Verify Answer button on this post if it answers your question. Thank You.
In reply to Cvetolin Shulev-XID:
The 66Ak2L06 processor, having IQN, DFE/JESD204B, Serdes as a subsystem does not have an RTOS example. This set of peripherals is controlled with a custom Linux application, and DSP transport program, called the RFSDK.
The RFSDK has specific example designs, 1, 2, and 4 on the TI website. Design 4 would be the closest example, the signal processing bypass can have two streams of
92.16Msps complex data, the Receiver can be setup for 15 of 16 bits of I and Q as a bypass, the LSB rounding results in the LSB not matching.
The design4 has a specific stream to channel structure for 1 or 2 Rx independent streams. The LMFSHD parameters are 22410 or 44410. There are 2 or 4 serdes lanes, the serdes line rate is 3.6864Gbps.
The transmit portion is also accurate to 15bits.
This is a streaming interface, ie once it is initialized the RFSDK will dump packets of data into the L3 buffer, which can be copied to DDR3 RAM, or saved with a file (the webpage control has some functions for this).
2 (LTE60 - 92,16Msps 16bit complex I and Q) sets are sent from DDR3 -> L3mem -> IQN -> DFE -> Serdes for Tx. Rx reverses this process.
To achieve the 15 bit bypass, once you have the RFSDK installed, and have used the JESD lane loopback (to test K2L by itself), You would set the remote FPGA parameters, and place it in loopback so that Tx data received on the FPGA, is then forwarded to the Rx data output.
This is a complicated example, (I avoided complex example), if you are not interested in stream processing.
There are PCIe Bar regions that can be shared between a remote device and the DSP memory. So if you want to extend the FPGA memory for read or write to the DSP device, PCIe is a simpler suggestion. Under the MCSDK, there are examples of a pcie driver. pdk_keystone2_xxxx/packages/ti/drv/pcie
Since there are two PCIe serdes, shared with Ethernet 2 and 3, you have to select the proper Boot Mode pins,
PCIe can transfer the memory desired.
In reply to Radio-Joe:
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