Part Number: TMS320C6678
Just a quick confirmation about input clock requirement in internal DDR3 PLL sysbsystem.Here is a snippet from C6678 datasheet. The requirement for DDR3 clock pins is 40Mhz(min), but because of PLLD, the clock can be smaller than 40Mhz just before PLLM input stage. I could not see any related restrictions in datasheet, so believe it should be ok, but please let me confirm just in case. Also, I would like to know the clock speed requirements/usage note about the inside of other PLL sysbsystems (Like main PLL, PA PLL, and etc..) if you have.
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The 40MHz lower limit is not associated with the PLL. That is the lower limit of the LJCB clock input buffer associated with the DDRCLKP/N pins. You cannot use a lower frequency then the 40MHz specified for the DDRCLKP/N input with the C6678.
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In reply to Bill Taboada:
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