RTOS/TMDSEVM6678: working with EDMA HWI and SYS/BIOS!

Part Number: TMDSEVM6678

Tool/software: TI-RTOS

I need to add an EDMA HWI to my working SYS/BIOS application and I'm having trouble adding the ISR. I have a working EDMA SPI example that I wanted to use with my application, but I'm guessing that there is some conflicts between CSL and BIOS. My application only goes to ISR once, and even after restarting the same application for a second time it doesn't go through the ISR unless a hard reset of the board is done, although the EDMA seems to be working and transferring data regardless!

Here is the application:

Void main()

{
	int i = 0;
	//Initialize EDMA for SPI transfer
	Setup_Edma_Init();
	Setup_SPI_Init();

	BIOS_start();     /* enable interrupts and start SYS/BIOS */
}

/*static task defined in app.cfg  */

void master_main()
{ 
    Int16 k,i,coreId,status;
    Task_Handle task;
    Error_Block eb;
    Task_Params params;

    
    Error_init(&eb);
    coreId = CSL_chipReadReg (CSL_CHIP_DNUM);
    System_printf("core ID %d\n",coreId);
    if(coreId == 0)
    {
     	Hwi_Params_init(&hwiParams);
    	hwiParams.eventId = 3;
    	hwiParams.arg = 1;
    	hwiParams.enableInt = FALSE;
    	// don't allow this interrupt to nest itself
    	hwiParams.maskSetting = Hwi_MaskingOption_SELF;
    	myHwi = Hwi_create(8, EdmaISR, &hwiParams, &eb);
    	if (myHwi == NULL) {
    		System_printf("Hwi_creat() failed!\n");
    	}
		 //Setup EDMA for SPI transfer
		 Setup_Edma_Init();

		 //Configure SPI and enable DMA interrupt support
		 Setup_SPI_Init();
		 Hwi_enableInterrupt(8);
		 //Enable EDMA for SPI transfer
		 Setup_Edma_Params_tx((Uint32)srcBuf);
		 Setup_Edma_Params_rx((Uint32)dstBuf);
		 /* Disable DMA Request */
		 ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 &=	~(CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT);

		 /* Enable DMA Request */
		 ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 |= CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT;
    }

   
	Task_Params_init(&params);
	for(i=0;i<BUFFER_NUMBER;i++)
	{
		params.priority = 8-i;
		params.arg0 = i;
		params.arg1 = coreId;

		task = Task_create(processDroplets, &params, &eb);
		if (task == NULL) {
			System_printf("Task_create() failed!\n");
			BIOS_exit(0);
		}
		

	}
 
		
}


void Enable_Edma_Channels(void)
{
   	// Enable channel
   	CSL_edma3HwChannelControl(hChannel0,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

   	// Enable channel
   	CSL_edma3HwChannelControl(hChannel1,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

}
void Setup_Edma_Init (void)
{

    // EDMA Module Initialization
	CSL_edma3Init(NULL);

 	// EDMA Module Open
    hModule = CSL_edma3Open(&moduleObj,CSL_TPCC_1,NULL,&EdmaStat);


	// SPI Tx Channel Open - Channel 2 for Tx (SPIXEVT)
	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
	chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = CSL_EDMA3_CHA_2;

	hChannel0 = CSL_edma3ChannelOpen(&ChObj0, CSL_TPCC_1, &chParam, &EdmaStat);
	chSetup.paramNum   = chParam.chaNum; //CSL_EDMA3_CHA_2;
    CSL_edma3HwChannelSetupParam(hChannel0,chSetup.paramNum);

	// SPI Rx Channel Open - Channel 3 for Rx (SPIREVT)
	chParam.regionNum  = CSL_EDMA3_REGION_GLOBAL;
	chSetup.que        = CSL_EDMA3_QUE_0;
	chParam.chaNum     = CSL_EDMA3_CHA_3;

	hChannel1 = CSL_edma3ChannelOpen(&ChObj1, CSL_TPCC_1, &chParam, &EdmaStat);
	chSetup.paramNum = chParam.chaNum; //CSL_EDMA3_CHA_3;
    CSL_edma3HwChannelSetupParam(hChannel1,chSetup.paramNum);

    Enable_Edma_Channels();
}

void Setup_SPI_Init (void)
{
    /* Reset SPI */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR0=
        CSL_SPI_SPIGCR0_RESET_IN_RESET<<CSL_SPI_SPIGCR0_RESET_SHIFT;

    /* Take SPI out of reset */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR0=
        CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET<<CSL_SPI_SPIGCR0_RESET_SHIFT;

    /* Configure SPI as master */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1=
        CSL_SPI_SPIGCR1_CLKMOD_INTERNAL<<CSL_SPI_SPIGCR1_CLKMOD_SHIFT|
        CSL_SPI_SPIGCR1_MASTER_MASTER<<CSL_SPI_SPIGCR1_MASTER_SHIFT;

    /* Configure SPI in 4-pin SCS mode */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIPC0=
        CSL_SPI_SPIPC0_SOMIFUN_SPI<<CSL_SPI_SPIPC0_SOMIFUN_SHIFT|
        CSL_SPI_SPIPC0_SIMOFUN_SPI<<CSL_SPI_SPIPC0_SIMOFUN_SHIFT|
        CSL_SPI_SPIPC0_CLKFUN_SPI<<CSL_SPI_SPIPC0_CLKFUN_SHIFT|
        CSL_SPI_SPIPC0_SCS0FUN1_SPI<<CSL_SPI_SPIPC0_SCS0FUN1_SHIFT;
    	//CSL_SPI_SPIPC0_SCS0FUN0_SPI<<CSL_SPI_SPIPC0_SCS0FUN0_SHIFT;

	/* Put SPI in Lpbk mode */
	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1 |=
		CSL_SPI_SPIGCR1_LOOPBACK_DISABLE<<CSL_SPI_SPIGCR1_LOOPBACK_SHIFT;

    /* Chose SPIFMT0 */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT1=
        CSL_SPI_SPIDAT1_DFSEL_FORMAT0<<CSL_SPI_SPIDAT1_DFSEL_SHIFT|
		CSL_SPI_SPIDAT1_WDEL_ENABLE<<CSL_SPI_SPIDAT1_WDEL_SHIFT|
		0x2<<CSL_SPI_SPIDAT1_CSNR_SHIFT;
		//CSL_SPI_SPIDAT1_CSHOLD_ENABLE<<CSL_SPI_SPIDAT1_CSHOLD_SHIFT;


    /* Configure for WAITEN=YES,SHIFTDIR=MSB,POLARITY=HIGH,PHASE=IN,CHARLEN=16*/
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIFMT[0]=
        CSL_SPI_SPIFMT_SHIFTDIR_MSB<<CSL_SPI_SPIFMT_SHIFTDIR_SHIFT|
        CSL_SPI_SPIFMT_POLARITY_LOW<<CSL_SPI_SPIFMT_POLARITY_SHIFT|
        CSL_SPI_SPIFMT_PHASE_NO_DELAY<<CSL_SPI_SPIFMT_PHASE_SHIFT|
        0xff<<CSL_SPI_SPIFMT_PRESCALE_SHIFT|
        0x8<<CSL_SPI_SPIFMT_CHARLEN_SHIFT|
		0x3f<<CSL_SPI_SPIFMT_WDELAY_SHIFT;


    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDELAY=
    		0x0F<<CSL_SPI_SPIDELAY_T2CDELAY_SHIFT;


    /* chose chip select active LOW:  bit 1 = high when no transfer occurs*/
        ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDEF=
        	//	CSL_SPI_SPIDEF_CSDEF0_HIGH<<CSL_SPI_SPIDEF_CSDEF0_SHIFT;
        		CSL_SPI_SPIDEF_CSDEF0_HIGH<<1;

	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 =
	CSL_SPI_SPIINT0_ENABLEHIGHZ_ENABLE<<CSL_SPI_SPIINT0_ENABLEHIGHZ_SHIFT|
	CSL_SPI_SPIINT0_OVRNINTENA_ENABLE<<CSL_SPI_SPIINT0_OVRNINTENA_SHIFT|
	CSL_SPI_SPIINT0_BITERRENA_ENABLE<<CSL_SPI_SPIINT0_BITERRENA_SHIFT|
	CSL_SPI_SPIINT0_DESYNCENA_ENABLE<<CSL_SPI_SPIINT0_DESYNCENA_SHIFT|
	CSL_SPI_SPIINT0_PARERRENA_ENABLE<<CSL_SPI_SPIINT0_PARERRENA_SHIFT|
	CSL_SPI_SPIINT0_TIMEOUTENA_ENABLE<<CSL_SPI_SPIINT0_TIMEOUTENA_SHIFT|
	CSL_SPI_SPIINT0_DLENERRENA_ENABLE<<CSL_SPI_SPIINT0_DLENERRENA_SHIFT;

    /* Enable communication */
    ((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1|=
        CSL_SPI_SPIGCR1_ENABLE_ENABLE<<CSL_SPI_SPIGCR1_ENABLE_SHIFT;

}

void Setup_Edma_Params_rx (Uint32 dstBuf)
{
	// Parameter Handle Open
	// Open all the handles and keep them ready

  	paramHandle1            = CSL_edma3GetParamHandle(hChannel1,CSL_EDMA3_CHA_3,&EdmaStat);
  	paramHandle1_reload     =(CSL_Edma3ParamHandle)(0x02724000);


    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,64);
	paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(0,TEST_ACNT );
	paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
	paramSetup.cCnt         = TEST_CCNT;
	paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,CSL_EDMA3_CHA_3,CSL_EDMA3_TCC_NORMAL, \
	      CSL_EDMA3_FIFOWIDTH_NONE,FALSE,CSL_EDMA3_SYNC_A,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);
	paramSetup.srcAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIBUF);

	paramSetup.dstAddr      = (Uint32)dstBuf;


	paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(paramHandle1_reload,0);

	CSL_edma3ParamSetup(paramHandle1,&paramSetup);
	CSL_edma3ParamSetup(paramHandle1_reload,&paramSetup);
}

void Setup_Edma_Params_tx (Uint32 srcBuf)
{
	// Parameter Handle Open
		// Open all the handles and keep them ready
		paramHandle0            = CSL_edma3GetParamHandle(hChannel0,CSL_EDMA3_CHA_2,&EdmaStat);
		paramHandle0_reload     =(CSL_Edma3ParamHandle)(0x02724080);
	    paramSetup.aCntbCnt     = CSL_EDMA3_CNT_MAKE(TEST_ACNT,(TEST_BCNT));
		paramSetup.srcDstBidx   = CSL_EDMA3_BIDX_MAKE(TEST_ACNT,0 );
		paramSetup.srcDstCidx   = CSL_EDMA3_CIDX_MAKE(0,0);
		paramSetup.cCnt         = TEST_CCNT;
		paramSetup.option       = CSL_EDMA3_OPT_MAKE(FALSE,FALSE,FALSE,TRUE,CSL_EDMA3_CHA_2,CSL_EDMA3_TCC_NORMAL, \
		      CSL_EDMA3_FIFOWIDTH_NONE,CSL_EDMA3_STATIC_DIS,CSL_EDMA3_SYNC_A,CSL_EDMA3_ADDRMODE_INCR,CSL_EDMA3_ADDRMODE_INCR);

		paramSetup.srcAddr      = (Uint32)(srcBuf);
		paramSetup.dstAddr      = (Uint32)&(((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIDAT0);
		//paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
		paramSetup.linkBcntrld  = CSL_EDMA3_LINKBCNTRLD_MAKE(paramHandle0_reload,0);

		CSL_edma3ParamSetup(paramHandle0,&paramSetup);
		CSL_edma3ParamSetup(paramHandle0_reload,&paramSetup);
}



void Close_Edma()
{
    CSL_FINST(hModule->regs->TPCC_SECR,TPCC_TPCC_SECR_SECR2,RESETVAL);
  	CSL_FINST(hModule->regs->TPCC_SECR,TPCC_TPCC_SECR_SECR3,RESETVAL);

 	CSL_edma3ChannelClose(hChannel0);
 	CSL_edma3ChannelClose(hChannel1);
 	CSL_edma3Close(hModule);
}

void EdmaISR(UArg arg0)
{

	static Uint16 i;
	regionIpr.region  = CSL_EDMA3_REGION_GLOBAL;
	regionIpr.intr    = 0;
	regionIpr.intrh   = 0;



	System_printf("Entered Edma Isr!\n");
	/* Clear pending interrupt*/
		CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, &regionIpr);


		HW_WR_REG32(EDMA_U_BASE_GLOBAL + EDMA_TPCC_ICR_RN,  0x000c);


	//Close EDMA channels/module
		Close_Edma();
		/* Disable DMA Request */
	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIINT0 &=	~(CSL_SPI_SPIINT0_DMAREQEN_ENABLE<<CSL_SPI_SPIINT0_DMAREQEN_SHIFT);
		 /* Disable communication*/
	((CSL_SpiRegsOvly) CSL_SPI_REGS)->SPIGCR1 &= ~(CSL_SPI_SPIGCR1_ENABLE_ENABLE<<CSL_SPI_SPIGCR1_ENABLE_SHIFT);

}

Could someone please tell me if I need to change anything here in order for it to work properly.

I would appreciate any help here.

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Hi,

RTOS team have been notified. Their feedback will be posted here.

Best Regards,
Yordan

0 lding over 6 years ago in reply to Yordan Kovachev

TI__Guru* 95265 points

Hi,

In the main routine, there is BIOS_start() without task creation. So I assume the task is in the void master_main(). I don't understand why Setup_Edma_Init() and Setup_SPI_Init() called both in main() and master_main().

The EDMA HWI registeration looks OK. Why you need to close EDMA channel in EDMA ISR? We don't have any SPI data example (only writer) for C6678 driver. So it is good to use EDMA simply move data from one location to other continously, to see is ISR is triggered once or always to isolate this is EDMA or SPI integration probelm.

Regards, Eric

0 MN over 6 years ago in reply to lding

Intellectual 600 points

Thanks for your reply Eric,

master_main is a task created statically. Calling Setups twice was a mistake, I did remove one, but it didn't have any effect.

I don't need to close EDMA in ISR. I was just trying to clear everything to see what happens for the second run. Nothing seems to have any effect. SPI and EDMA seem to be working continuously and I see data in memory getting updated. The only problem is that it does not go in the ISR more than once after resetting the board. Even when I restart the same application, it wouldn't go through ISR.

So, you don't think my use of CSL library and BIOS, HWI has any conflicts?!

Thanks.

0 MN over 6 years ago in reply to MN

Intellectual 600 points

Does anyone know if my use of CSL library and BIOS, HWI has any conflicts?!

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RTOS/TMDSEVM6678: working with EDMA HWI and SYS/BIOS!