Using TMDSEVM6657 board I have found UPP phisical lines are not correspond to schematic description:
If I use UPP mode DUPLEX 1 for 16-bit transmission, port 0 (I) [15:8] bits are always zeros but lower bits are valid. Another way in DUPLEX 0 port 1 (Q) transmits only higher 8 valid bits. In conclusion I have found port 0 [15:8] bus lines are actually port 1 [7:0] lines and vice versa!
((CSL_UppRegs *)_RegBase)->UPCTL =
(CSL_UPP_UPCTL_MODE_DUPLEX1 << CSL_UPP_UPCTL_MODE_SHIFT) | (CSL_UPP_UPCTL_CHN_TWO << CSL_UPP_UPCTL_CHN_SHIFT) |
(CSL_UPP_UPCTL_DPWA_FULL << CSL_UPP_UPCTL_DPWA_SHIFT) |
(CSL_UPP_UPCTL_IWA_16BIT << CSL_UPP_UPCTL_IWA_SHIFT) | (CSL_UPP_UPCTL_DRA_DOUBLE << CSL_UPP_UPCTL_DRA_SHIFT) |
(CSL_UPP_UPCTL_DPWB_12BIT << CSL_UPP_UPCTL_DPWB_SHIFT) |
(CSL_UPP_UPCTL_IWB_FULL << CSL_UPP_UPCTL_IWB_SHIFT) | (CSL_UPP_UPCTL_DRB_DOUBLE << CSL_UPP_UPCTL_DRB_SHIFT);
