• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 102 subscribers
  • Views 831 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H14: DSP SPI Boot Throughput

Jack Carter
Prodigy 190 points
Part Number: 66AK2H14

I am attempting to determine the maximum data rate that can be achieved when booting over a SPI interface. I understand that there are many factors involved. My preliminary findings suggest the maximum transfer rate is around 1Mbyte/sec. I am currently testing with an EVMK2Hx development board. The image that I have created contains a prepended Boot Parameter Table that successfully changes the SPI clock rate from the default PLL Bypass rate of around 200KHz to 35MHz. The image is clearly loaded in 128 byte blocks as observed on a logic analyzer. There is an inter-byte delay within each packet of around 540 nanoseconds. This seems consistent with what I have read in other posts. In addition, there is an inter-block delay of around 9.2 microseconds. The image successfully boots as observed by UART output and LED activity. Are the delays that I'm observing consistent with the RBL design and is the SPI interface limited to data rates around 1Mbyte/sec?

Thanks for your support.

Jack

  • 0
    TI__Guru**** 161600 points
    Hi Jack,

    I've asked the design team to elaborate. Their feedback will be posted directly here.

    Best Regards,
    Yordan
  • 0
    TI__Guru** 114410 points
    Jack,

    When the 66AK2H14 chip was designed the ROM bootloader didn`t have any boot time/throughout requirements to meet as the assumption was that the ROM bootloader willl load a small secondary bootloader that will configure the PLL, DDR and SPI interface to speed up the boot process for the OS (typically Linux but also supports RTOS) so what you are seeing is consistent with the implementation of the boot ROM. Also addition SPI throughput optimization can be obtained by using EDMA based SPI driver implementation so that the max data rate of close to the interface supported 50 Mhz can be used to transfer the boot image.

    If boot times are critical for your application then TI recommendation is to use a secondary bootloader to attain higher transfer speeds as ROM is designed for booting consistently from different boot media and not necessarily for fast boot.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Prodigy 190 points

    Rahul, 

    Thanks for your reply. We are evaluating other interfaces to meet time critical boot requirements but wanted to confirm the limitations of  SPI. 

    Regards, 

    jack