66AK2L06: 66AK2L06 CVDD1 supply

Btw does it mean the power sequencing is correct if i able to connected to the DSP chip using emulator?

Thanks. I now able to connect to the chip using emulator and debug using CCS. I am using the same register setting as the evm board. However my chip not able to boot from the flash. I check through boundary scan, it seem like my SPI nor flash and DDR3 memory was connected correctly and i able to run some test to tested them out through the JTAG and boundary scan. Is there any step i have missed out?I loaded the .gph extension file into the boot flash, could it support? or i need to convert the .gph file to binary before loaded them to binary? Thanks

I am uisng linux.

Second question, I try to debug through emulator, by sequence, the image stored in the internal ram first right? then the image will move to DDR3? I now not even able to write/read from DDR3. I follow the register setting as defined in the spreadsheet provided by TI for 2 x  DDR3 (MT41K256M16TW-107 IT:P). How do i ensure i set the correct register for initialization?

Or write leveling is need to set first? i am using fly-by topology for DDR3 routing. Hope you can give me a hand on this. Thanks a lot!

Hi Yordan,

We able to find the gal files and loaded to css to test memory read write. However we get this error listed below. Do you know what is the error Error -1205 @ 0x80000000? Do i need to change the memory block location? 

arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):           

arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz)              

arm_A15_0: GEL Output: DDR3 PLL Setup ...         

arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.

arm_A15_0: GEL Output: DDR3A initialization complete    

arm_A15_0: GEL Output: Memory Test Write Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100, value: 0x0xAAAAAAAA ...

arm_A15_0: GEL Output: Memory Test Read Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100 ...             

arm_A15_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1205 @ 0x80000000) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)     

ddr3A_write_read_test() cannot be evaluated.     

Target failed to read 0x80000000             

               at read_data=*((unsigned int *) mem_location) [tcievmk2l_arm.gel:2406]

               at ddr3A_write_read_test()arm_A15_0: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)

arm_A15_0: Trouble Reading Register REG_SYSTEM_MMU_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)    

arm_A15_0: Failed CPU Reset (SW): (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.222.0)