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TMDSEVM6657: one of CDCE62005 output channel has a problem. The other channels is working well.

Yun-Seok Cho
Intellectual 440 points
Part Number: TMDSEVM6657
Other Parts Discussed in Thread: CDCE62005

Hello!

I made my own board based on TMDSEVM6657.

My board is not exactly same but basically almost same with TMDSEVM6657..

 

I got a problem between DSP and CDCE62005.

 

The pin map between them is like below.

CDCD62005                  DSP

CH0                 ->        SRIOSGMIICLK : 250MHz

CH1                 ->          Not used

CH2                 ->          DDRCLK: 66Mhz

CH3                ->           CORECLK: 100MHz

CH4                ->            Not used

 

 

I add a port to communicate directly to the  CDCE62005 through SPI pin.

This port is only used for programing the CDCE62005.

Normally the SPI pin  from CDCE62005  is connected to FPGA.

 

The configuration of CDCE62005 is like below.

This value was copied from the EVM FPGA code.

0: 0xE9840320
1: 0x69840301      
2: 0xE9020302
3: 0xE9840303
4: 0x69860314
5: 0x101C0BE5
6: 0x04BE0F06
7: 0xFD0037F7

 

After the board has been booted up using with EVM FPGA code , I could see a sinewave coming only from ch2, ch3  of CDCE62005. 

In case of ch0, I could also see sinewave from it but it was for very short time.

This FPGA code is not exactly same with the EVM's.  

A part of the code  is  attached as a name of "modificaiton.zip".

 And If I use my FPGA code,  I can see sinewave from  all of ch0 , ch2 and ch3.

This code is different than the "modificaiton.zip".

Could you please look over the attached file of "my_code.zip".

This code is very simple and just make a connection between external port and CDCE62005 SPI pin.

Using with this code, I can access to the register of CDCE62005 through SPI.

From the register, I have confirmed that the PLL was locked.

 

If I ask you again, what kind of condition makes the output of  CDCE62005 off.

 

Regards

Yun-Seok Cho

 

my_code.zip

 

 modification.zip

 

 

  • 0
    TI__Guru 65405 points
    I've forwarded your query to the hardware design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Mastermind 42545 points
    Hi Yun-Seok Cho,
    I loaded the registers you provided above into the CDCE62005 tool and checked the values listed. According to the tool, you are selecting 100MHz for both channel 0 and channel 3. The tool states that there is no least common multiply able to generate both 250MHz and 100MHz. Where did you get the register values provided?
    Regards, Bill
  • 0 in reply to Bill Taboada
    Intellectual 440 points

    Hi!

    The register value was from the FPGA code supplied by 'eInfoChips'.

    •https://www.einfochips.com/partnerships-and-alliances/system-partnerships/texas-instruments/tms320c6657-evm/

    The below figure is  a part of the FPGA code from which I derived the value.
     
    Actually, When I put the value of  'E9840320' to the register  '0', what I could see is a 100Mhz sinewave , not a 250Mhz sinewave.
     
     
    My problem is not a number of frequency.
     
     
    My problem is like this.
     
    I have worked with the FPGA code provided by "einfochips" but I edit it little bit  for my system.
     
    While the system booting, I can see a clock output from CH0,CH2 and CH3 of CDCE62005.
     
    But it was very short time that the CH0 generates clock.
     
    After booing completed, CH2 and CH3 normally generate clock but CH0 stop generating clock.
     
    I'm still  trying to fix this problem.
     
    No progress!
     
    Regards
    Yun-Seok Cho
     

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points
    Hi Yun-Seok Cho,
    It sounds like you can read and write the registers in the CDCE62005. After the clock from CH0 stops, please read all eight of the registers so we can see the status of the device. Can you also provide details on all the connections to the CH0 output? If there is some instability in your system that is causing the clock to stop, we will have to get the clocking team supporting the CDCE62005 on the thread.
    Regards, Bill
  • 0 in reply to Bill Taboada
    TI__Mastermind 42545 points
    Hi Yun-Seok Cho,
    I have not received any additional questions. Did you have any addition questions on this issue? I will close the thread but if you reply it will reopen.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Intellectual 440 points

    Hello!

    The PCB what I'm working with was dead while debugging.

    After fixing this problem, I'll give you the register value of CDCE62005.

    Please, do not close this thread.

    Regards

    Yun-Seok Cho

     

     

     

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points
    Hi Yun-Seok,
    I will leave it open. Let me know when you have more information.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Intellectual 440 points

    Hello!

    Now I have the register value of CDCE62005.

    Please, refer to the below image.

     

    1. First image

    After booting is completed and pll lock is high, I read the value from the CDCE62005.

    The value is showing on the first image.

    The register for CH0 is NULL and I can't see  clock signal from the pin #27 of CDCE62005.

     

    2. Second image

    After booting is completed and pll lock is high, write parameter to the CDCE62005 and read it again from the CDCE62005.

    The value is showing on the second image.

    I can see also clock singal  from the pin #27 of CDCE62005. The clock signal was fine.

     

    I dont't know the reason why the value of CH0 is null.

     

    Regards

    Yun-Seok Cho

    <#1, After Booting is completed, PLL Lock is 'High'>

     

    <#2, After writing  to the CDCE62005 and reading from the one>

     

     

     

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points

    Hello Yun-Seok,

    Please explain how the registers are programmed the first time when booting the board. Is writing the value for channel 0 the first access to the first access to the device after the board begins to boot? After you rewrite the register values, does the clock remain stable or does it shut down after time?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 440 points

    Hello!

     

    I did program a FPGA code which has a few of simple functions.

    it just supplys power to each device and connects the SPI port of CDCE62005 to a external header.

    The externall header is wired to a MCU board.

    I  read and write the CDCE62005 through the MCU board.

    At the first time, I wrote the register value to the CDCE62005 in this way and used to boot the system.

     

    The FPGA source code supplied by 'einfochips' was edited in order to make a connection between CDCE62005 on the target borad and the external MCU board.

    After booting complted and rewriting the register value to the CDCE62005, the clock signal was stable.

     

    Here is a capture image what i'm focusing on.

    While  the system booting, I captured a few of signal which are connected  to CDCE62005.

    Before FPGA reading the regsiger of CDCE62005, the clock signal was normally generated.

    At the first rising edge of the SPI_LE signal, the clock signal was disappeared.

     

    I don't understand why this happens.

     

    Regards

    Yun-Seok Cho

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points

    Hi Yun-Seok, 

    Based on the information that you posted, it appears that there must be a problem with the first access.  If I understand correctly, you are reading the registers at boot time and that first read is corrupting the value of the CH0 register.  Can you compare the accesses at boot time with the accesses you use to read the registers later?  Since the registers of the CDCE62005 can be written to non-volatile memory, this access only needs to be written once. Can this be access from the FPGA be removed from the boot process?

    Regards, Bill

  • 0 in reply to Yun-Seok Cho
    Intellectual 440 points

    Hello!

    After edit the FPGA code to stop reading the CDCE62005 from FGPA, I can see the clock signal of CH0 after DSP booting up.

    I don't know why this problem happens.

    I guess there is a bug on my FPGA code.

     

    Anyway I also think that the register value of the CDCE62005 on my board is not correct.

    could you please let me know the register value of the CDCE62005 using with a C6657 EVM ?

     

    It will be very helpful for me to understand how to set the register value for the CDCE62005.

     

    Regards

    Yun-Seok Cho

     

     

     

     

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points
    Hi Yun-Seok,
    I'm still working on getting those register values.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Intellectual 440 points

    Hi Bill,

     

    I'm waiting for your answer.

     

    Regads

    Yun-Seok Cho

  • 0 in reply to Yun-Seok Cho
    TI__Mastermind 42545 points
    Hi Yun-Seok,
    My apologies for the delay. I have contacted the designer and he should be providing the information early this week. I will post the register values as soon as I receive them.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    TI__Mastermind 42545 points

    Hi Yun-Seok,

    Again I apologize for the delay. The register values initialized in the FPGA for use by the clock generator are as follows.

    E9840320, E9840301, E90E0302, E9060303, E9060314, 10000BE5, 04FE03E6, FD993B47, 80FE03E6, 84FE03E6, 0000008e;

    When loaded into the tool for the CDCE62005 that generates the attached ini file. This should generate the frequencies specified in the schematic for the EVM.

    Regards, Bill

    CDCE62005_gauss_evm_fpga.ini