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tms320c6678: DDRRESET termination

Keith Nicholas
Mastermind 39500 points
Part Number: TMS320C6678

Hello Team,

Posting on behalf of customer:

I have seen differing advice on the termination of the DDRRESET line from the TMS320C6678. On one reference design it is pulled up to VTT on another it is pulled up to 1.5V and on the Keystone Wiki, it recommends pulling it down to GND. We currently have it implemented with DDRRESET pulled up to VTT.
During normal operation the DDRRESET line was only getting to 0.5V. To test if the TMS320C6678 is actively driving the line, I removed the pullup and noted that the line does not get driven high. Looking at the Micron Spec for the memory they recommend DDRRESET = 0.8 * VDD just like in one of the TMS320C6678 manuals.
I personally believe that the line should be pulled up to 1.5V. What is the factory recommendation, and why?

Thanks,
Keith N.
AFA OH/wPA

  • 0
    TI__Guru**** 161600 points
    Hi Keith,

    On one reference design it is pulled up to VTT on another it is pulled up to 1.5V and on the Keystone Wiki, it recommends pulling it down to GND


    Can you share which reference designs do you refer to? In TMS320C6678 EVM the DDRRESET signal or DSP0_DDR3_EMRESETN (ball E11) directly connected to the ddr chip, without any pulls:
    wfcache.advantech.com/.../TMDSEVM6678Lx_EVM_REV_3_0_DSN.pdf

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 35 points

    If you look at the schematic that you are linking to, on page 13 there is R66 a 4.7k pullup to 1.5V.

    Thanks,

    Dan

  • 0 in reply to Dan Elliott
    TI__Guru**** 161600 points
    Hi Dan,

    You're correct. I've missed this.
    Also you're correct that this is very misleading. In TMS320C6678 they follow the DDR Design Requirements (sprabi1b) document --> pull-up the ddrreset.

    For K2H & K2E evms, which use the same manual DDR Design Requirements (sprabi1b) for designing the ddr connections, they follow the schematic checklist & connect to ground through pulldown.

    Perhaps the pulls (whether pullup or pulldown) are required so that the reset level is stable during power on and the DDR controller can establish the reset level at the desired time without glitches on the line before that.

    I believe the wiki is the least updated document, so I'd recommend to follow the TMS320C6678 EVM & what is recommended in the DDR Design Requirements. I am looping the design team to confirm.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Dan,

    Early C6678 EVM schematics had it terminated incorrectly to VTT.  This was corrected before production EVM release.  The DDRRESET pin should have a pull-up to the DDR supply or a pull-down to ground so that valid CMOS levels are always present on the RESET to the SDRAM devices - even when the processor is not fully powered.

    Some system implementations can use a pull-up so that the SDRAM can be held in self-refresh mode while power is removed from the KeyStone device.  This is not the standard configuration for KeyStone-I and KeyStone-II devices.  Operation of the board with the processor power removed has been too difficult in these systems.  Therefore, a pull-down should be implemented on the DDRRESET for these devices.  We have devices in other product lines that do support this.

    Tom