Linux/DM3730: where is mmu initialized ?

Hi Tvestoliln,

Attached is the A9-cortex which compiles for me.

I am not sure if any of these registers are not aomptible with A8.

Doesn't the compiler should complain ?

If you know about some open source mmu initialization for mmu please let me know.

Thank you,

Ran

init_mmu.S

Did you ever get your MMU running?  I'm having trouble getting the L1 Dcache enabled on a DM3730.  I'm not using Linux.

dcache_disable();
icache_disable();
icache_invalidate();
tlb_invalidate(); /* this is both iTLB and dTLB */
init_mmu_ttb(); /* this is page table set up and MMU register programming */
mmu_enable();
dcache_invalidate();
dcache_enable();
dcache_preload();

Those are the steps I take, but in dcache_preload() data writes are going to SDRAM and not to L1 dcache.  L2 cache is diabled.  Since the L1 dcache is allocate on read, I load a word, overwrite it, and expect the write to go to L1 and not to SDRAM, but my writes go to SDRAM.  It appears the MMU is working ok, but the dcache is not taking data.

No OS.  Custom MLO post u-boot.  So I have to set up page tables (just 4096 1MB section level 1 pages, cacheable, bufferable, full access, VA=PA (TEX=000b, C=1, B=1, write-back, no read allocate) myself and enable L1 Dcache.  L2 cache is disabled, L1 Icache is disabled.  I'm testing for L1 Dcache enabled, by enabling it, Load/Store to 24 cachelines word by word, disable C-bit in Control Register and then printing.  I *expect* to print the SDRAM data and not the L1 Dcache data since I've disabled C-bit and TRM claims with C-bit disable there are no accesses to L1.  I would expect the L1 Dcache data to be valid and dirty, but up to me to clean and/or invalidate since I'm write-back.  The TRM claims the L1 Dcache is *only* read allocate which is why I do a load then a store to get the SDRAM data in to the L1 Dcache.  So it looks like the L1 Dcache is acting like write-through *or* it's not actually enabled.  Which is odd when control register C-bit is on and I have page tables set up.