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Linux/AM3359: GPMC configuration

Brian Lojeck
Prodigy 40 points
Other Parts Discussed in Thread: SYSCONFIG

I'm editing an existing design based on an AM335x uProc. The system was set up using the SDK.

I need to make changes to the configuration registers listed in the TLM (specifically, to set  bit 0 of register GPMC_SYSCONFIG (offset x"10") to 0 to set the clock to free-running).

However, for the life of me, I cannot find any reference to HOW these registers are changed. The team I'm working with doesn't remember.

I've been digging through startup guides and manuals for a day. Please help.

Many thanks!

  • 0
    TI__Guru**** 170625 points
    Hi Brian,

    GPMC_SYSCONFIG register is modified by u-boot in the below file:

    u-boot-2017.01/arch/arm/mach-omap2/mem-common.c

    writel(0x00000008, &gpmc_cfg->sysconfig);

    Other GPMC registers are also modified in below file:

    u-boot-2017.01/drivers/mtd/nand/omap_gpmc.c

    Regards,
    Pavel
  • 0
    TI__Guru**** 393215 points
    GPMC_SYSCONFIG bit 0 is set to 0 by default. Please specify what Linux version you are using.
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    Regarding linux kernel, GPMC_SYSCONFIG register is modified in below file:

    linux-4.9.59/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

    static struct omap_hwmod_class am33xx_gpmc_hwmod_class


    The rest of the GPMC registers are modified in below file:

    linux-4.9.59/drivers/memory/omap-gpmc.c


    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 40 points

    Biser Gatchev-XID said:
    GPMC_SYSCONFIG bit 0 is set to 0 by default. Please specify what Linux version you are using.

    From the boot log:

    [    0.000000] Linux version 3.14.43-g875c69b (user@ubuntu) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #4 Fri Dec 23 11:43:55 PST 2016

     

    Pavel Botev said:


    u-boot-2017.01/arch/arm/mach-omap2/mem-common.c
    ...
    u-boot-2017.01/drivers/mtd/nand/omap_gpmc.c

    Pavel Botev said:


    linux-4.9.59/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
    ...
    linux-4.9.59/drivers/memory/omap-gpmc.c

    Thanks! So that I can avoid too many dumb questions in the future, where should I have looked to find the information on setting these registers?

  • 0 in reply to Brian Lojeck
    Prodigy 40 points

    OK, one more clueless question:

    In the two files referenced, I assume I should set the '0' bit in both? So that it's set both by the boot loader, and then by the linux configuration?

    So in mem-common.c, the indicated line:

    /* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);

    this is writing to the gpmc_cfg struct sysconfig register the value x"08" in order to set smart-idle "on", take the chip out of soft reset, and set the clock to free running, yes? So, I don't need to edit this file, if I'm seeing things right.

    In the linux setup file indicated (omap_hwmod_33xx_45xx_ipblock_data.c), the lines indicates are:

    /* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.syss_offs	= 0x14,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
	.name		= "gpmc",
	.sysc		= &gpmc_sysc,
};

    to set the system for a free-running clock here, do I need to remove SYSC_HAS_AUTOIDLE from the .sysc_flags OR statement? Or is there something else I need to do?

    Thanks for your help.

  • 0
    Prodigy 40 points
    Disregard my question. I misunderstood the purpose of that control bit. I assumed it would make the GPMC clock signal non-gated, but it apparently is for an internal clock setting.
  • 0 in reply to Brian Lojeck
    TI__Guru**** 170625 points
    Brian,

    To enable/disable GPMC clock, you should use PRCM CM_PER_GPMC_CLKCTRL register. See also AM335x TRM, section

    7.1.2.2 GPMC Clock and Reset Management

    Regards,
    Pavel