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Linux/AM3359: Interfacing Xilinx Artix-7 family(XC7A200T) with am3359 GPMC

Murugan S22
Expert 1240 points
Part Number: AM3359

Tool/software: Linux

Hello All,

                         I'm trying to interface xilinx FPGA with am3359 via GPCM(CS1) on custom board based on AM3359 icev2.A nand flash is also connected to the GPMC(CS0).I added fpga and nand as the child nodes of gpmc in the device tree.Is the device tree configuration and enabling the respective fpga drivers enough to access the fpga?.Also I would like to write a .bin file to fpga from the  user space.Is it possible?. The board is is the final phase of design.I'm looking for a head start.Any  information would be really helpful.TIA

Regards,

Murugan S

  • 0
    TI__Genius 9510 points
    Please attached the device tree file.
  • 0 in reply to Marcus Cooksey
    Expert 1240 points

    Fullscreen am335x-icev2.txt Download 
    /*
 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * AM335x ICE V2 board
 * http://www.ti.com/tool/tmdsice3359
 */

/dts-v1/;

#include "am33xx.dtsi"

/ {
	model = "TI AM3359 ICE-V2";
	compatible = "ti,am3359-icev2", "ti,am33xx";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	chosen {
		stdout-path = &uart3;
	};

	vbat: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	vtt_fixed: fixedregulator1 {
		compatible = "regulator-fixed";
		regulator-name = "vtt";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
	};

	leds-iio {
		status = "disabled";
		compatible = "gpio-leds";
		led-out0 {
			label = "out0";
			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out1 {
			label = "out1";
			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out2 {
			label = "out2";
			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out3 {
			label = "out3";
			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out4 {
			label = "out4";
			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out5 {
			label = "out5";
			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out6 {
			label = "out6";
			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-out7 {
			label = "out7";
			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	/* Tricolor status LEDs */
	leds1 {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&user_leds>;

		led0 {
			label = "status0:red:cpu0";
			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "cpu0";
		};

		led1 {
			label = "status0:green:usr";
			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led2 {
			label = "status0:yellow:usr";
			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led3 {
			label = "status1:red:mmc0";
			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc0";
		};

		led4 {
			label = "status1:green:usr";
			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led5 {
			label = "status1:yellow:usr";
			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};
	gpio-decoder {
		compatible = "gpio-decoder";
		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
			<&pca9536 2 GPIO_ACTIVE_HIGH>,
			<&pca9536 1 GPIO_ACTIVE_HIGH>,
			<&pca9536 0 GPIO_ACTIVE_HIGH>;
		linux,axis = <0>; /* ABS_X */
		decoder-max-value = <9>;
	};

	/* Dual mac ethernet application node on icss */
	pruss_eth {
		compatible = "ti,am3359-prueth";
		pruss = <&pruss>;
		sram = <&ocmcram>;
		interrupt-parent = <&pruss_intc>;
		status = "disabled";

		pinctrl-0 = <&pruss_eth_default>;
		pinctrl-names = "default";

		pruss_emac0: ethernet-mii0 {
			phy-handle = <&pruss_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss_emac1: ethernet-mii1 {
			phy-handle = <&pruss_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&am33xx_pinmux {
	user_leds: user_leds {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
		>;
	};

	mmc0_pins_default: mmc0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
		>;
	};

	i2c0_pins_default: i2c0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
		>;
	};

	spi0_pins_default: spi0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */
			AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
		>;
	};

	uart3_pins_default: uart3_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
		>;
	};
	
	 uart4_pins_default: uart4_pins_default {
                pinctrl-single,pins = <
                        AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */
                        AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */
                >;
        };


	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1, RMII mode */
			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_crs.rmii1_crs_dv */
			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))	/* rmii1_refclk.rmii1_refclk */
			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd0.rmii1_rxd0 */
			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd1.rmii1_rxd1 */
			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxerr.rmii1_rxerr */
			AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd0.rmii1_txd0 */
			AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd1.rmii1_txd1 */
			AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txen.rmii1_txen */
			/* Slave 2, RMII mode */
			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))

			/* Slave 2 reset value */
			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
		>;
	};

	pruss_mdio_default: pruss_mdio_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x88c, (PIN_OUTPUT | MUX_MODE5))		/* gpmc_clk.pr1_mdio_mdclk */
			AM33XX_IOPAD(0x888, (PIN_INPUT  | MUX_MODE5))		/* gpmc_csn3.pr1_mdio_data */
			AM33XX_IOPAD(0x89c, (PIN_INPUT_PULLUP | MUX_MODE7))	/* gpmc_ben0_cle.gpio2_5 */
			/* disable CPSW MDIO */
			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | MUX_MODE7))	/* mdio_data.gpio0_0 */
			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLUP | MUX_MODE7))	/* mdio_clk.gpio0_1 */
		>;
	};

	pruss_eth_default: pruss_eth_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x8a0, (PIN_INPUT  | MUX_MODE2))	/* dss_data0.pr1_mii_mt0_clk */
			AM33XX_IOPAD(0x8b4, (PIN_OUTPUT | MUX_MODE2))	/* dss_data5.pr1_mii0_txd0 */
			AM33XX_IOPAD(0x8b0, (PIN_OUTPUT | MUX_MODE2))	/* dss_data4.pr1_mii0_txd1 */
			AM33XX_IOPAD(0x8ac, (PIN_OUTPUT | MUX_MODE2))	/* dss_data3.pr1_mii0_txd2 */
			AM33XX_IOPAD(0x8a8, (PIN_OUTPUT | MUX_MODE2))	/* dss_data2.pr1_mii0_txd3 */
			AM33XX_IOPAD(0x8cc, (PIN_INPUT  | MUX_MODE5))	/* dss_data11.pr1_mii0_rxd0 */
			AM33XX_IOPAD(0x8c8, (PIN_INPUT  | MUX_MODE5))	/* dss_data10.pr1_mii0_rxd1 */
			AM33XX_IOPAD(0x8c4, (PIN_INPUT  | MUX_MODE5))	/* dss_data9.pr1_mii0_rxd2 */
			AM33XX_IOPAD(0x8c0, (PIN_INPUT  | MUX_MODE5))	/* dss_data8.pr1_mii0_rxd3 */
			AM33XX_IOPAD(0x8a4, (PIN_OUTPUT | MUX_MODE2))	/* dss_data1.pr1_mii0_txen */
			AM33XX_IOPAD(0x8d8, (PIN_INPUT  | MUX_MODE5))	/* dss_data14.pr1_mii_mr0_clk */
			AM33XX_IOPAD(0x8dc, (PIN_INPUT  | MUX_MODE5))	/* dss_data15.pr1_mii0_rxdv */
			AM33XX_IOPAD(0x8d4, (PIN_INPUT  | MUX_MODE5))	/* dss_data13.pr1_mii0_rxer */
			AM33XX_IOPAD(0x8d0, (PIN_INPUT  | MUX_MODE5))	/* dss_data12.pr1_mii0_rxlink */
			AM33XX_IOPAD(0x8e8, (PIN_INPUT  | MUX_MODE2))	/* dss_pclk.pr1_mii0_crs */

			AM33XX_IOPAD(0x840, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a0.pr1_mii_mt1_clk */
			AM33XX_IOPAD(0x850, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a4.pr1_mii1_txd0 */
			AM33XX_IOPAD(0x84c, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a3.pr1_mii1_txd1 */
			AM33XX_IOPAD(0x848, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a2.pr1_mii1_txd2 */
			AM33XX_IOPAD(0x844, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a1.pr1_mii1_txd3 */
			AM33XX_IOPAD(0x860, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a8.pr1_mii1_rxd0 */
			AM33XX_IOPAD(0x85c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a7.pr1_mii1_rxd1 */
			AM33XX_IOPAD(0x858, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a6.pr1_mii1_rxd2 */
			AM33XX_IOPAD(0x854, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a5.pr1_mii1_rxd3 */
			AM33XX_IOPAD(0x874, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_wpn.pr1_mii1_txen */
			AM33XX_IOPAD(0x864, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a9.pr1_mii_mr1_clk */
			AM33XX_IOPAD(0x868, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a10.pr1_mii1_rxdv */
			AM33XX_IOPAD(0x86c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a11.pr1_mii1_rxer */
			AM33XX_IOPAD(0x878, (PIN_INPUT  | MUX_MODE5))	/* gpmc_ben1.pr1_mii1_rxlink */
			AM33XX_IOPAD(0x8ec, (PIN_INPUT  | MUX_MODE2))	/* lcd_ac_bias_en.pr1_mii1_crs */
			AM33XX_IOPAD(0x870, (PIN_INPUT  | MUX_MODE5))	/* gpmc_wait0.pr1_mii1_col */
		>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_default>;

	status = "okay";
	clock-frequency = <400000>;

	tps: power-controller@2d {
		reg = <0x2d>;
	};

	tpic2810: gpio@60 {
		compatible = "ti,tpic2810";
		reg = <0x60>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9536: gpio@41 {
		compatible = "ti,pca9536";
		reg = <0x41>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins_default>;

	sn65hvs882@1 {
		compatible = "pisosr-gpio";
		gpio-controller;
		#gpio-cells = <2>;

		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;

		reg = <1>;
		spi-max-frequency = <1000000>;
		spi-cpol;
	};

	spi_nor: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "winbond,w25q64", "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "u-boot";
			reg = <0x80000 0x100000>;
			read-only;
		};

		partition@2 {
			label = "u-boot-env";
			reg = <0x180000 0x20000>;
			read-only;
		};

		partition@3 {
			label = "misc";
			reg = <0x1A0000 0x660000>;
		};
	};

};

&tscadc {
	status = "okay";
	adc {
		ti,adc-channels = <1 2 3 4 5 6 7>;
	};
};

#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1326000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1144000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&vmmc_reg>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins_default>;
};

&gpio0 {
	/* Do not idle the GPIO used for holding the VTT regulator */
	ti,no-reset-on-init;
	ti,no-idle-on-init;

	p7 {
		gpio-hog;
		gpios = <7 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "FET_SWITCH_CTRL";
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins_default>;
	status = "okay";
};
&uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_default>;
        status = "okay";
};

&gpio3 {
	p4 {
		gpio-hog;
		gpios = <4 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "PR1_MII_CTRL";
	};

	p10 {
		gpio-hog;
		gpios = <10 GPIO_ACTIVE_HIGH>;
		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
		output-high;
		line-name = "MUX_MII_CTL1";
	};
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <3>;
	phy-mode = "rmii";
	dual_emac_res_vlan = <2>;
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
	dual_emac;
};

&phy_sel {
	rmii-clock-ext;
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&pruss_soc_bus {
	status = "okay";

	pruss: pruss@4a300000 {
		status = "okay";

		pru0: pru@4a334000 {
			status = "okay";
		};

		pru1: pru@4a338000 {
			status = "okay";
		};
	};
};

&pruss_mdio {
	pinctrl-0 = <&pruss_mdio_default>;
	pinctrl-names = "default";
	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>; /* PHY datasheet states 1uS min */
	status = "disabled";

	pruss_eth0_phy: ethernet-phy@1 {
		 reg = <1>;
	 };

	pruss_eth1_phy: ethernet-phy@3 {
		 reg = <3>;
	 };
};



&gpmc {
    status = "okay";
    pinctrl-names = "default";
/*    pinctrl-0 = <&nandflash_pins_s0>;*/
    ranges = <0 0 0x08000000 0x2000000>;    /* CS0: 16MB for NAND */
    nand@0,0 {
        compatible = "ti,omap2-nand";
        reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
        interrupt-parent = <&gpmc>;
        interrupts = <0 0>, /* fifoevent */
                 <1 0>;    /* termcount */
        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
        ti,nand-ecc-opt = "bch8";
        ti,elm-id = <&elm>;
        nand-bus-width = <8>;
        gpmc,device-width = <1>;
        gpmc,sync-clk-ps = <0>;
        gpmc,cs-on-ns = <0>;
        gpmc,cs-rd-off-ns = <44>;
        gpmc,cs-wr-off-ns = <44>;
        gpmc,adv-on-ns = <6>;
        gpmc,adv-rd-off-ns = <34>;
        gpmc,adv-wr-off-ns = <44>;
        gpmc,we-on-ns = <0>;
        gpmc,we-off-ns = <40>;
        gpmc,oe-on-ns = <0>;
        gpmc,oe-off-ns = <54>;
        gpmc,access-ns = <64>;
        gpmc,rd-cycle-ns = <82>;
        gpmc,wr-cycle-ns = <82>;
        gpmc,bus-turnaround-ns = <0>;
        gpmc,cycle2cycle-delay-ns = <0>;
        gpmc,clk-activation-ns = <0>;
        gpmc,wr-access-ns = <40>;
        gpmc,wr-data-mux-bus-ns = <0>;
        /* MTD partition table */
        /* All SPL-* partitions are sized to minimal length
         * which can be independently programmable. For
         * NAND flash this is equal to size of erase-block */
        #address-cells = <1>;
        #size-cells = <1>;
        partition@0 {
            label = "NAND.SPL";
            reg = <0x00000000 0x000020000>;
        };
        partition@1 {
            label = "NAND.SPL.backup1";
            reg = <0x00020000 0x00020000>;
        };
        partition@2 {
            label = "NAND.SPL.backup2";
            reg = <0x00040000 0x00020000>;
        };
        partition@3 {
            label = "NAND.SPL.backup3";
            reg = <0x00060000 0x00020000>;
        };
        partition@4 {
            label = "NAND.u-boot-spl-os";
            reg = <0x00080000 0x00040000>;
        };
        partition@5 {
            label = "NAND.u-boot";
            reg = <0x000C0000 0x00100000>;
        };
        partition@6 {
            label = "NAND.u-boot-env";
            reg = <0x001C0000 0x00020000>;
        };
        partition@7 {
            label = "NAND.u-boot-env.backup1";
            reg = <0x001E0000 0x00020000>;
        };
        partition@8 {
            label = "NAND.kernel";
            reg = <0x00200000 0x00800000>;
        };
        partition@9 {
            label = "NAND.file-system";
            reg = <0x00A00000 0x0F600000>;
        };
    };
	fpga{

		reg = <2 0 0>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpmc,sync-clk-ps = <20000>; /* Minimum clock period for synchronous mode, in picoseconds */

		gpmc,cs-on-ns = <0>; /* Assertion time */
		gpmc,cs-rd-off-ns = <100> ; /* Read deassertion time */
		gpmc,cs-wr-off-ns = <40>; /* Write deassertion time */

		/* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
		gpmc,adv-on-ns = <0>; /* Assertion time */
		gpmc,adv-rd-off-ns = <20>; /* Read deassertion time */
		gpmc,adv-wr-off-ns = <20>; /* Write deassertion time */

		/* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
		gpmc,we-on-ns = <20>; /* Assertion time */
		gpmc,we-off-ns = <20>; /* Deassertion time */

		/* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
		gpmc,oe-on-ns = <20>; /* Assertion time */
		gpmc,oe-off-ns = <100>; /* Deassertion time */

		/* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
		gpmc,page-burst-access-ns = <20>; /* Multiple access word delay */
		gpmc,access-ns = <80>; /* Start-cycle to first data valid delay */
		gpmc,rd-cycle-ns = <120>; /* Total read cycle time */
		gpmc,wr-cycle-ns = <60>; /* Total write cycle time */

		gpmc,device-width = <2>; /* Total width of device(s) connected to a GPMC
		chip-select in bytes. The GPMC supports 8-bit
		and 16-bit devices and so this property must be
		1 or 2. */

		gpmc,sync-read; /* Enables synchronous read. Defaults to asynchronous is this is not set. */
		gpmc,sync-write; /* Enables synchronous writes. Defaults to asynchronous is this is not set. */


		};
};

  • 0 in reply to Marcus Cooksey
    Expert 1240 points
    Hi Marcus,
    I have attached the dts file(rename to .txt because i cant upload the dts file as such).Please have a look.
    Regards,
    Murugan S
  • 0 in reply to Murugan S22
    TI__Mastermind 30526 points
    Murugan,

    I didn't see pin mux data in your DTS. Have a look here for an example in the AM437x family:

    git.ti.com/.../am437x-gp-evm.dts

    As far as writing the data, this is beyond the scope of the support we can provide. The GPMC driver will use the data in the DTS file to configure the GPMC, but there is no "driver" per se to write the data to that space. You will need to develop this methodology as part of your system design.
  • 0 in reply to RonB
    Expert 1240 points

    Hi Ron,
    Thanks for the input.I referred the link you shared and enabled pinmuxing for gpmc:

            gpmc_pins: gpmc_pins {
                    pinctrl-single,pins=<
                            AM33XX_IOPAD(0x800,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad0.gpmc.ad0*/
                            AM33XX_IOPAD(0x804,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad1.gpmc.ad1*/
                            AM33XX_IOPAD(0x808,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad2.gpmc.ad2*/
                            AM33XX_IOPAD(0x80C,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad3.gpmc.ad3*/
                            AM33XX_IOPAD(0x810,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad4.gpmc.ad4*/
                            AM33XX_IOPAD(0x814,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad5.gpmc.ad5*/
                            AM33XX_IOPAD(0x818,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad6.gpmc.ad6*/
                            AM33XX_IOPAD(0x81C,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad7.gpmc.ad7*/
                            AM33XX_IOPAD(0x820,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad8.gpmc.ad8*/
                            AM33XX_IOPAD(0x824,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad9.gpmc.ad9*/
                            AM33XX_IOPAD(0x828,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad10.gpmc.ad10*/
                            AM33XX_IOPAD(0x82C,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad11.gpmc.ad11*/
                            AM33XX_IOPAD(0x830,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad12.gpmc.ad12*/
                            AM33XX_IOPAD(0x834,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad13.gpmc.ad13*/
                            AM33XX_IOPAD(0x838,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad14.gpmc.ad14*/
                            AM33XX_IOPAD(0x83C,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_ad15.gpmc.ad15*/

                            AM33XX_IOPAD(0x870,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_wait0*/
                            AM33XX_IOPAD(0x874,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_wpn*/
                            AM33XX_IOPAD(0x878,PIN_OUTPUT|MUX_MODE0)/*gpmc_ben1*/
                            AM33XX_IOPAD(0x87C,PIN_OUTPUT|MUX_MODE0)/*gpmc_csn0*/
                            AM33XX_IOPAD(0x884,PIN_OUTPUT|MUX_MODE0)/*gpmc_csn2*/
                            AM33XX_IOPAD(0x88C,PIN_INPUT_PULLUP|MUX_MODE0)/*gpmc_clk*/
                            AM33XX_IOPAD(0x890,PIN_OUTPUT|MUX_MODE0)/*gpmc_advn_ale*/
                            AM33XX_IOPAD(0x894,PIN_OUTPUT_PULLUP|MUX_MODE0)/*gpmc_oen_ren*/
                            AM33XX_IOPAD(0x898,PIN_OUTPUT_PULLUP|MUX_MODE0)/*gpmc_wen*/
                            AM33XX_IOPAD(0x89C,PIN_OUTPUT_PULLUP|MUX_MODE0)/*gpmc_ben0_cle*/
                    >;
            };



    Is this correct?And also I couldn't understand the difference between PIN_OUTPUT and PIN_OUTPUT_PULLUP.

    Regards,
    Murugan S

  • 0 in reply to Murugan S22
    TI__Mastermind 30526 points
    Murugan S,

    This is starting to look much better. The _PULLUP enables the internal PULLUP within the device. Whether it is needed or not depends on your board implementation and use. Please refer to the TRM for more details.

    Thanks.