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Linux/AM3359: AM3359 processor with Artix-7 FPGA via GPMC 16 bit asynchronous multiplexed Address & Data bus

Mobin P K
Expert 1035 points
Part Number: AM3359

Tool/software: Linux

Sir,

We have planned to interface the TI AM3359 processor with Artix-7 FPGA via GPMC 16 bit asynchronous multiplexed address & data bus and referring the timing diagram of  "GPMC and Multiplexed NOR Flash -

Asynchronous Write / Read - Single word" present in AM3359 data sheet section 7.7.1.2. 

Timing diagram of  burst write / read for the same mode is not available in the data sheet.

Whether the GPMC - Multiplexed NOR Flash - Asynchronous mode will support burst Write / Read ?

How would be the timing diagram, when GPMC data transmission & reception is going to implement along with DMA concept ?

Kindly share the timing diagram of "GPMC and Multiplexed NOR Flash - Asynchronous Mode with DMA" .

 

Regards,

Mobin P K

  • 0
    TI__Guru**** 393215 points
    Hi,

    See Figure 7-24 in the datasheet. Make sure you also read section 7.1 in the AM335x TRM Rev. P:

    • GPMC supports the following interface protocols when communicating with external memory or external devices:
    – Asynchronous read/write access
    – Asynchronous read page access (4-8-16 Word16)
    – Synchronous read/write access
    – Synchronous read burst access without wrap capability (4-8-16 Word16)
    – Synchronous read burst access with wrap capability (4-8-16 Word16)
  • 0 in reply to Biser Gatchev-XID
    Expert 1035 points
    Sir,

    Whether the GPMC - Multiplexed NOR Flash - Asynchronous mode will support burst Write / Read ?

    thanks
    Mobin P K
  • 0 in reply to Mobin P K
    TI__Guru**** 393215 points
    I think that I clearly listed the supported modes of operation in my previous post.
  • 0 in reply to Biser Gatchev-XID
    Expert 1035 points
    Sir,

    Is it possible to implement the DMA along with GPMC (16 bit asynchronous Multiplexed address and data) which is connected with external FPGA & TI processor.

    How would be the timing diagram, when GPMC data transmission & reception is going to implement along with DMA concept ?

    thanks

    Mobin
  • 0 in reply to Mobin P K
    TI__Guru**** 393215 points
    It's possible to trigger an XDMA request from the FPGA. This will not reflect on the GPMC timings in any way. DMA transfers are internal to the AM335x.
  • 0 in reply to Biser Gatchev-XID
    Expert 1035 points
    thanks for your reply,

    How would be the timing diagram, when GPMC data transmission & reception is going to implement along with DMA concept ?

    what is the maximum throughput i can achieve using DMA + GPMC with an external FPGA ?

    Kindly share the calculation if its possible

    thanks
    Mobin P K
  • 0 in reply to Mobin P K
    TI__Guru**** 393215 points
    I already replied to your question about timing (see my post above). We don't have performance benchmarks for your use case.