DDR3 - 512M configuartion

ranchu

Guru 20755 points

Hello,

I would like to ask for your suggestion as to how to configure DDR of 512M total (2 banks of 256M) in custom board.

#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ <<-- should be left the same as EVM ?
#define PHYS_DRAM_1_SIZE 0x10000000 /* 256 MB */ <<-- in EVM is 0x20000000 (512M)
#define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */ <<-- should be left the same as EVM ?
#define PHYS_DRAM_2_SIZE 0x10000000 /* 256 MB */ <<-- in EVM is 0x20000000 (512M)

How should I configure the LISA registers for my configuration (should it be the same as with EVM) ?

#define PG2_1_DMM_LISA_MAP__0 0x80540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__1 0xA0540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__2 0x80540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__3 0xA0540300 <<-- should be left the same as EVM ?

Thanks!
Ran

over 10 years ago

0 Pavel Botev over 10 years ago

TI__Guru**** 170625 points

Hi Ran,

Ran S. said:
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ <<-- should be left the same as EVM ?
#define PHYS_DRAM_1_SIZE 0x10000000 /* 256 MB */ <<-- in EVM is 0x20000000 (512M)
#define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */ <<-- should be left the same as EVM ?
#define PHYS_DRAM_2_SIZE 0x10000000 /* 256 MB */ <<-- in EVM is 0x20000000 (512M)

The above configuration is fine for 512MB DDR3 system. Note that you can also make it with:

#define PHYS_DRAM_2 0x90000000 - you can use this, if you do not have something in the 0x9xxxxxxx addresses, something like CMEM, DSP, firmware, etc

Ran S. said:

How should I configure the LISA registers for my configuration (should it be the same as with EVM) ?

#define PG2_1_DMM_LISA_MAP__0 0x80540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__1 0xA0540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__2 0x80540300 <<-- should be left the same as EVM ?
#define PG2_1_DMM_LISA_MAP__3 0xA0540300 <<-- should be left the same as EVM ?

From EZSDK 512MB memory map:

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM816x_Board

Following code programs the LISA registers for 512MB physical memory.

/* Program the DMM to for 512MB (interleaved) configuration */

__raw_writel(0x0, DMM_LISA_MAP__0); /* Register 0 is unused */

__raw_writel(0x0, DMM_LISA_MAP__1); /* Register 1 is unused */

__raw_writel(0x80540300, DMM_LISA_MAP__2); /* Register 2 maps 0x80000000 to 0x00000000, length 512MB */

__raw_writel(0xA0540300, DMM_LISA_MAP__3); /* Register 3 maps 0xA0000000 to 0x00000000, length 512MB */

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM814x_Board

Modified values for 512 MB

#define PG2_1_DMM_LISA_MAP__2 0x80540300

#define PG2_1_DMM_LISA_MAP__3 0xA0540300

Best regards,
Pavel

0 Pavel Botev over 10 years ago in reply to Pavel Botev

TI__Guru**** 170625 points

See also the below e2e threads:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/260461.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/305051.aspx

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/186056.aspx

Regards,
Pavel

0 ranchu over 10 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

I have set the registers as you write above, but I get something strange in u-boot
I do see in boot log that NAND: 512M print, but on writing values to 0x8000000 offset, I read the same values in 0x90000000. Do you understand why this happens ?

TI-MIN#mtest 0x80000000 0x80100000 0xa5a5a5a5 1
Pattern A5A5A5A5 Writing... Reading...Tested 1 iteration(s) with 0 errors.
TI-MIN#md 0x90000000
90000000: a5a5a5a5 a5a5a5a6 a5a5a5a7 a5a5a5a8 ................
90000010: a5a5a5a9 a5a5a5aa a5a5a5ab a5a5a5ac ................
90000020: a5a5a5ad a5a5a5ae a5a5a5af a5a5a5b0 ................
90000030: a5a5a5b1 a5a5a5b2 a5a5a5b3 a5a5a5b4 ................
90000040: a5a5a5b5 a5a5a5b6 a5a5a5b7 a5a5a5b8 ................
90000050: a5a5a5b9 a5a5a5ba a5a5a5bb a5a5a5bc ................
90000060: a5a5a5bd a5a5a5be a5a5a5bf a5a5a5c0 ................
90000070: a5a5a5c1 a5a5a5c2 a5a5a5c3 a5a5a5c4 ................
90000080: a5a5a5c5 a5a5a5c6 a5a5a5c7 a5a5a5c8 ................
90000090: a5a5a5c9 a5a5a5ca a5a5a5cb a5a5a5cc ................
900000a0: a5a5a5cd a5a5a5ce a5a5a5cf a5a5a5d0 ................
900000b0: a5a5a5d1 a5a5a5d2 a5a5a5d3 a5a5a5d4 ................
900000c0: a5a5a5d5 a5a5a5d6 a5a5a5d7 a5a5a5d8 ................
900000d0: a5a5a5d9 a5a5a5da a5a5a5db a5a5a5dc ................
900000e0: a5a5a5dd a5a5a5de a5a5a5df a5a5a5e0 ................
900000f0: a5a5a5e1 a5a5a5e2 a5a5a5e3 a5a5a5e4 ................

Thanks,

Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

This test works fine on the DM814x EVM:

TI-MIN#md 0x90000000
90000000: 6c6d41d5 20897929 79400148 e07bc969    .Aml)y. H.@yi.{.
90000010: 8e12a6d6 17b61390 00961094 96961c16    ................
90000020: 0b68e968 89401b7d 697979cb 696961f2    h.h.}.@..yyi.aii
90000030: 041697d2 85839680 10a49682 031634ce    .............4..
90000040: 6aeb296d 5b2060f1 692049c9 684b482f    m).j.` [.I i/HKh
90000050: 969e44d9 b60e469a dc948296 12128a90    .D...F..........
90000060: 24e94bf9 404bc881 0229ed7d 692a6969    .K.$..K@}.).ii*i
90000070: 1095831c 16965596 96ae84c6 c4d39685    .....U..........
90000080: 7c606b6a 79686141 c909586d 28610bc8    jk`|AahymX....a(
90000090: b60e5296 97807c9e 54961cc6 b0960614    .R...|.....T....
900000a0: 21253d65 70605160 0968e168 69696a7b    e=%!`Q`ph.h.{jii
900000b0: 948692a4 b0901795 1295963e cea682c2    ........>.......
900000c0: 41c86940 69602160 686d2169 e229a941    @i.A`!`ii!mhA.).
900000d0: 17909e9f 065416b4 d6908616 93b21284    ......T.........
900000e0: 2a492060 2848494d 3b290929 e9694021    ` I*MIH().);!@i.
900000f0: d4944e8c 96b8d096 52823892 4796a796    .N.......8.R...G
TI-MIN#md 0x80000000
80000000: 9eb75d97 3ea73587 a792f792 b29ebe56    .]...5.>....V...
80000010: 96a49292 94b297dc 9e90980c 9714e406    ................
80000020: f696b6b6 95b6bb06 94f6be55 a0b69a84    ........U.......
80000030: b6868297 169684f6 96969494 12909710    ................
80000040: 97b7a61e 96779ef6 91969592 c696f69e    ......w.........
80000050: a486848e 1c9496b6 97e48090 b29636b6    .............6..
80000060: 9696969c d5dcbebe f6b6e4b7 d6569687    ..............V.
80000070: cac39682 8690939c 96968617 96849686    ................
80000080: f7359606 b636e6d2 b6e61617 96f993df    ..5...6.........
80000090: b0069ed1 01cc83e6 9cb3d696 96961490    ................
800000a0: fcdb94d6 97f79e57 96b79f1e d7b796d4    ....W...........
800000b0: 94979794 16869496 b2948c96 f696c496    ................
800000c0: 979ed63a b28f9684 be5687ce b6b792c2    :.........V.....
800000d0: 9690119a 0696a0b2 86969414 b4a116d4    ................
800000e0: b7a64396 9495b29a 82b79406 b6ae06b4    .C..............
800000f0: 968694b6 36868696 8502c68e 839e9294    .......6........
TI-MIN#mtest 0x80000000 0x80100000 0xa5a5a5a5 1
Pattern A5A5A5A5 Writing... Reading...Tested 1 iteration(s) with 0 errors.
TI-MIN#md 0x90000000
90000000: 6c6d41d5 20897929 79400148 e07bc969    .Aml)y. H.@yi.{.
90000010: 8e12a6d6 17b61390 00961094 96961c16    ................
90000020: 0b68e968 89401b7d 697979cb 696961f2    h.h.}.@..yyi.aii
90000030: 041697d2 85839680 10a49682 031634ce    .............4..
90000040: 6aeb296d 5b2060f1 692049c9 684b482f    m).j.` [.I i/HKh
90000050: 969e44d9 b60e469a dc948296 12128a90    .D...F..........
90000060: 24e94bf9 404bc881 0229ed7d 692a6969    .K.$..K@}.).ii*i
90000070: 1095831c 16965596 96ae84c6 c4d39685    .....U..........
90000080: 7c606b6a 79686141 c909586d 28610bc8    jk`|AahymX....a(
90000090: b60e5296 97807c9e 54961cc6 b0960614    .R...|.....T....
900000a0: 21253d65 70605160 0968e168 69696a7b    e=%!`Q`ph.h.{jii
900000b0: 948692a4 b0901795 1295963e cea682c2    ........>.......
900000c0: 41c86940 69602160 686d2169 e229a941    @i.A`!`ii!mhA.).
900000d0: 17909e9f 065416b4 d6908616 93b21284    ......T.........
900000e0: 2a492060 2848494d 3b290929 e9694021    ` I*MIH().);!@i.
900000f0: d4944e8c 96b8d096 52823892 4796a796    .N.......8.R...G
TI-MIN#md 0x80000000
80000000: a5a5a5a5 a5a5a5a6 a5a5a5a7 a5a5a5a8    ................
80000010: a5a5a5a9 a5a5a5aa a5a5a5ab a5a5a5ac    ................
80000020: a5a5a5ad a5a5a5ae a5a5a5af a5a5a5b0    ................
80000030: a5a5a5b1 a5a5a5b2 a5a5a5b3 a5a5a5b4    ................
80000040: a5a5a5b5 a5a5a5b6 a5a5a5b7 a5a5a5b8    ................
80000050: a5a5a5b9 a5a5a5ba a5a5a5bb a5a5a5bc    ................
80000060: a5a5a5bd a5a5a5be a5a5a5bf a5a5a5c0    ................
80000070: a5a5a5c1 a5a5a5c2 a5a5a5c3 a5a5a5c4    ................
80000080: a5a5a5c5 a5a5a5c6 a5a5a5c7 a5a5a5c8    ................
80000090: a5a5a5c9 a5a5a5ca a5a5a5cb a5a5a5cc    ................
800000a0: a5a5a5cd a5a5a5ce a5a5a5cf a5a5a5d0    ................
800000b0: a5a5a5d1 a5a5a5d2 a5a5a5d3 a5a5a5d4    ................
800000c0: a5a5a5d5 a5a5a5d6 a5a5a5d7 a5a5a5d8    ................
800000d0: a5a5a5d9 a5a5a5da a5a5a5db a5a5a5dc    ................
800000e0: a5a5a5dd a5a5a5de a5a5a5df a5a5a5e0    ................
800000f0: a5a5a5e1 a5a5a5e2 a5a5a5e3 a5a5a5e4    ................
TI-MIN#

I suspect you have some HW DDR3 issue. Please double check your HW DDR design. Refer to the device datasheet and EVM schematics.

Regards,
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

I try to understand the memory map...

Doesn't the LISA configuration as you gave before, will create the following system memory map:

0x80000000-0x8FFFFFFF --> map 256M to 0x00000000

0xA0000000-0xAFFFFFFF --> map 256M to 0x00000000

If so, 0x90000000 is not part of this and so the information there is not relevant if I am correct, right ?

Regards,
Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Refer to the below resources:

DM814x TRM, sections 6.2.1.6 Section Mapping, 6.3.4 Address Management Using LISA Sections

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM814x_Board

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/186056.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/343423.aspx

Regards,
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Thanks Pavel,

This links are helpful, and I reviewed them, especially

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM814x_Board which is more readable then the LISA section in TRM.

Anyhow, I just wanted to verify that when I accessed 0x90000000 it was actually wrong doing , because 0x9000000 is not mapped to physical memory according to the above configuration, and therefor finding there the DDR values should probably be ignored. What do you think ?

Thank
Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Ran S. said:
Anyhow, I just wanted to verify that when I accessed 0x90000000 it was actually wrong doing , because 0x9000000 is not mapped to physical memory according to the above configuration, and therefor finding there the DDR values should probably be ignored.

I think you are correct.

Regards,
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

I wanted to ask one more on this if I may.

Is there any reason why we change the mapping for 512M (2 banks of 256M) to 0xa0000000 instead of 0xc0000000 ?

Regards,

Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Ran S. said:
Is there any reason why we change the mapping for 512M (2 banks of 256M) to 0xa0000000 instead of 0xc0000000 ?

I think the reason for using 0xA0000000 instead of 0xC0000000 in the EZSDK 512 MB memory map is the IPC_SR_FRAME_BUFFERS (shared region for video buffers) at start address 0xAB000000.

P.S. You can make different configurations from the default one. See the DM814x TRM, DMM chapter.

Regards,
Pavel

0 ranchu over 9 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

I am using DVRRDK 4.1.0.2.

According to DM81xx_DVR_RDK_Install_Guide.pdf the default memory configuration is 512M (although the EVM has 1G, which means that it does not use the full DDR capabilities in EVM!) :

"By default memory configuration selected for different platforms are
• DM816x: DDR=1GB, Linux mem=256MB
• DM814x: DDR=512MB, Linux mem=128MB
• DM810x: DDR=512MB, Linux mem=128MB"

As far as I understand, it also means that I can work with the same memory settings (=without modifications) with my custom board which has total of 512M (2 banks of 256M) each.
This are the defautl settings of LISA is DVRRDK (ddr_defs_ti814x.h):

#define DDR_MEM_512M // For McFW default configuration of 512 MB
#ifdef DDR_MEM_512M
/*
* TI814X PG2.1 DMM LISA MAPPING
* 512 section
*/

#define PG2_1_DMM_LISA_MAP__0 0x80540300
#define PG2_1_DMM_LISA_MAP__1 0xA0540300
#define PG2_1_DMM_LISA_MAP__2 0x80540300
#define PG2_1_DMM_LISA_MAP__3 0xA0540300

Note that PG2_1_DMM_LISA_MAP__2 & PG2_1_DMM_LISA_MAP__3 above has the same values as for the ezsdk 512M configuration .
Do you think It is necessary to change PG2_1_DMM_LISA_MAP__0 & PG2_1_DMM_LISA_MAP__1 to 0 instead of the above values ?

Thanks for any feedback,

Ran

0 Pavel Botev over 9 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

Ran S. said:
Do you think It is necessary to change PG2_1_DMM_LISA_MAP__0 & PG2_1_DMM_LISA_MAP__1 to 0 instead of the above values ?

You can use the RDK 512MB default settings. I do not think it is necessary to change PG2_1_DMM_LISA_MAP__0 & PG2_1_DMM_LISA_MAP__1 to 0, as this two registers has lower priority from 2 & 3. See DM814x TRM, section 6.2.1.6 Section Mapping

Regards,
Pavel

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DDR3 - 512M configuartion