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Running CCS5 code from SD EVM811x

Alfred Espinosa
Intellectual 570 points

Hi,

I'm currently have a diagnostings code in CCS5.5(linux) and i'm trying to run it from SD card.

Since this does a diagnostics, this will not load in the DDR of the board, will be in the Internal ram of the processor.

I have an MLO File And the U-Boot running for a kernel running from SD, but i'm not very sure which changes i have to do for using the other internal memory

The Diagnostics code has a GEL which is functional with the debugger, and that seems to do the Map of the pins. I would be grateful to have any reference, documentation, or any "how to start".

Thanks in advance

  • 0
    TI__Guru**** 170625 points
    Hi Alfred,

    From what I understand you want to transfer the code from CCS (GEL file + *.out file) to SD card? And you need to run this code from u-boot, linux kernel or user space?

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 570 points

    I need to run this in the SRAM, because this code does diagnostics of the DDR ram in the board, without kernel.

    Everything else seems what i want to do.

    So, i want to "replicate" what the debugger does, with GEL file, but with an sd card. I hope that makes sense

  • 0 in reply to Alfred Espinosa
    TI__Guru**** 170625 points
    Alfred,

    I think you can implement this DDR test into the 1st stage bootloader (u-boot.min.sd/MLO). This MLO is loaded into OCMC RAM0 and initialize DDR. You can put this DDR test right after the DDR init.

    See the below wiki page, it is for DM814x, but should be similar to the DM811x device:
    processors.wiki.ti.com/.../Understanding_u-boot-min_startup_for_DM814x

    u-boot/board/ti/ti811x/evm.c

    void s_init(u32 in_ddr)
    {
    /* TODO: Revisit enabling of I/D-cache in 1st stage */
    #if 0
    icache_enable();
    dcache_enable();
    #endif

    /*
    * Disable Write Allocate on miss to avoid starvation of other masters
    * (than A8).
    *
    * Ref TI811X Erratum: TODO
    */
    l2_disable_wa();

    /* Can be removed as A8 comes up with L2 enabled */
    l2_cache_enable();
    unlock_pll_control_mmr();
    /* Setup the PLLs and the clocks for the peripherals */
    prcm_init(in_ddr);
    #ifdef CONFIG_TI811X_CONFIG_DDR
    if (!in_ddr)
    config_ti811x_ddr(); /* Do DDR settings */
    test_ddr(); --------------> put your ddr test here
    #endif
    }

    Note that MLO has size limitations, so keep in mind that when building/loading the new MLO. The size of the internal RAM in TI811x is 128 KiB, out of which 18 KiB at the end is used by the ROM code. This placed a limit of 110 KiB on the size of the U-Boot binary which the ROM code can transfer to the internal RAM.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 570 points
    thank you Pavel, let me check about this and get back to you later