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DDR3 Initialization - write leveling

Jonathan Journo
Intellectual 475 points
Other Parts Discussed in Thread: AM3874

Hi,

I am working with a custom board with a DM8148 and 4 16-bit DDR3 memories of type DDR3-1333 connected to DDR0/DDR1.

We have encountered some issues to read/write to the DDR3. But, if slowing down the DDR clock speed to 100Mhz, the RD/WR problem still exist but the faults are statistically less frequent. So my 2 cents idea that is a timing configuration problem and not a logic hardware connection issue.

 

So, I tried to configure the DDR3 PHY using the instructions from the wiki link:

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

From the spreadsheet RatioSeed I fill our custom parameters: 

Parameters
DDR3 clock frequency 333.5 MHz
Invert Clkout 0
Trace Length (inches)
Byte 0 Byte 1 Byte 2 Byte 3
CK trace 1.9 1.9 1.43 1.43
DQS trace 1.26 1.2 0.9 0.7
Seed values (per byte lane)
WR DQS 9 A 8 B
RD DQS 34 34 34 34
RD DQS GATE 77 76 65 5F
Seed Values to input to program
WR DQS 9
RD DQS 34
RD DQS GATE 6C

(the DDR3 layout rules seems to be OK.)

The numbers in green are inputs from my custom board layout and the speed of my DDR3 (I used half the clock speed 667Mhz /2 and reduced CL by two to match datasheet requirements.)

But it seems the RD DQS colored in red is a value that is not influenced by my configuration values in (green).

In other words, the WR DQS and the RD DQS GATE are computed regarding my custom board trace length (inches) but the RD DQS is not computed. It is hard coded to the value 0x34. maybe this value is only good for the mistral evm.

1/ How can I set the RD DQS value for my custom board.?

I modify the GEL file with the output of the spreadsheet and then I runned the DDR3_slave_ratio_search_auto.out application to know how to tune my GEL file with a more accurate configuration but the output of the API was all ZEROES.

2/ Is the program use the auto leveling chip feature to configure the DQS delays?

3/ What does means all the zeroes? (may be the program could not converge to any values / leveling failed).

4/ Is the source code of the DDR3_slave_ratio_search_auto executable could be share with us? so I can investigate the issue deeper.

I repeat the same steps with a lower ddr clock -100Mhz and also a higher one -400Mhz also I tried other RD DQS values. But the same problem was encountered.

I tried also to enable the invert clkout feature. (also in the GEL file), no success

Any help from TI support team or other users will be welcomed,

Thanks,

Jonathan.

  • 0
    Intellectual 345 points

    Hi Jonathan,

    I already did my costume board with am3874 and face the same problem. I was working with a ddr3- 1600 and was able only to work with 200Mhz before setting the dd3 timings registers. After that i reach 533Mhz and i will try to configure the byte lanes registers to reach 800Mhz.

    What you have to do is:

    Use this spreadsheet : http://processors.wiki.ti.com/index.php/File:DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0.zip

    You must fill with your memory part number timing information and it will give you some register configurations to fill it on your ddr_def.h

      

  • 0 in reply to Guilherme Haas
    Intellectual 360 points

    Hi  Guilherme Haas,

    I am Facing the same problem with my Custom DM8148 Board. i have gone through http://processors.wiki.ti.com/index.php/File:DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0.zip

    but i find

    DDRPHYCR  in cpu.h as

    #define EMIF4_0_DDR_PHY_CTRL_1        (EMIF4_0_CFG_BASE + 0xE4)

    #define EMIF4_1_DDR_PHY_CTRL_1        (EMIF4_1_CFG_BASE + 0xE4)

    And

    DDRIOCTRL in cpu.h as

    #define DDR0_IO_CTRL            (CTRL_BASE + 0x0E04)
    #define DDR1_IO_CTRL            (CTRL_BASE + 0x0E08)

    these Values are defined in different Files and it seems more of a Address then Value. while Excel give the Values.

    Any idea where to Put the values of above registers.

    Br,

    KP

  • 0 in reply to KP Singh
    Intellectual 345 points

    Hi PK, 

    These are the location and files where you must change.

    Uboot folder : arch/arm/include/asm/arch-ti81xx/

    There are two files to be change inside this folder  .

    First one is clocks_ti814x.h where you have to change the value at line 67 :

     # define DDR_M (pg_val_ti814x(666,1066))

    you have to enter with the double of your frequency (200MHz -> 400, 400MHz -> 800, 533Mhz -> 1066, 800Mz -> 1600).

    Second one is in ddr_defs_ti814x.h where you have to change the timming values for your frequency.

    I add some "ifdefs" to change easily among diferentes frequencies. In this file you have to enter with the results of DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.

    #ifdef DDR3_200_TOTH
    #define DDR3_EMIF_READ_LATENCY 0x00173209
    #define DDR3_EMIF_TIM1 0x0AAAD4DB
    #define DDR3_EMIF_TIM2 0x682F7FDA
    #define DDR3_EMIF_TIM3 0x501F82BF
    #define DDR3_EMIF_REF_CTRL 0x00000C30
    #define DDR3_EMIF_SDRAM_CONFIG 0x61C011B2
    #define DDR3_EMIF_SDRAM_ZQCR 0x50074BE1
    #endif
    

    #ifdef DDR3_400_TOTH
    

    #define DDR3_EMIF_READ_LATENCY 0x0017020C
    

    #define DDR3_EMIF_TIM1 0x0AAAD4DB
    

    #define DDR3_EMIF_TIM2 0x402F7FDA
    

    #define DDR3_EMIF_TIM3 0x505F83FF
    

    #define DDR3_EMIF_REF_CTRL 0x00000C30
    

    #define DDR3_EMIF_SDRAM_CONFIG 0x61C63232
    

    #define DDR3_EMIF_SDRAM_ZQCR 0x500750C6
    

    #endif 
    

    

    #ifdef DDR3_533_TOTH
    

    #define DDR3_EMIF_READ_LATENCY 0x0017020C
    

    #define DDR3_EMIF_TIM1 0x0EEF266B
    

    #define DDR3_EMIF_TIM2 0x403F7FDA
    

    #define DDR3_EMIF_TIM3 0x505F855F
    

    #define DDR3_EMIF_REF_CTRL 0x0000103D
    

    #define DDR3_EMIF_SDRAM_CONFIG 0x61C63232
    

    #define DDR3_EMIF_SDRAM_ZQCR 0x500750C8
    

    #endif
    


    

    If you do not get any results take a look  at the LISA MAP register to configure the correct configuration.
    


    

    1563.clocks_ti814x.h8713.ddr_defs_ti814x.h
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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