Dm8148 CPSW RGMII clock delay

Stephen Turner said:

OK, we found the functionality in the GMII_SEL register (p735 in the datasheet).  Its not clear weather it affects both the TX and the RX side?.  

I asked this very same question several months ago before the GMII_SEL register was documented in the TRM @ http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/155890.aspx  It's still unclear if affects the RX side.  It definitely affects the GTXCLK for my board, and without it the PHY fails to transmit data, but does receive data.

You may also be interested to hear that the GTXCLK internal delay can be controlled via SYSBOOT[7] (still undocumented as far as I know), and this affects booting from gigabit. See my post @ http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/170318.aspx where a TI employee explained SYSBOOT[7]

Hi Kyle

Thanks for your insight.  Its a shame I did not find your posts earlier.

In the end, we found that we had to disable the EMAC RGMII delay and enable the delay in our PHY (VSC8601) on both the RX and TX side for things to work.

Interesting about SYSBOOT7.  I was wondering if they had something like that.

-steve

Hi Stephen,

Would you please tell me how to set the external and internal delay in detail?

Thank you

Bob