Turning off emac module on DM8168

Asaf,

The EMAC0/1 modules belongs to the always-on (ALWON) power domain, and this power domain can not be transitioned to OFF, only the clock domain (ETHERNET) can be OFF (clock signals gated).

DM816x TRM, chapter 18 PRCM

18.6.2 Power Domains Management
PRCM contains a set of memory-mapped PM-type registers for those functional power domains. These registers allow software to configure define the states of the physical domains under each functional domain state. All domain transitions are fully software controllable. Always ON power domain is never transitioned from the ON power state.

18.6.3.1 Power-Down Sequence - I see you are aligned with that sequence. Look at step 5, we have no ALWON PWRSTCTRL register.

If only modules need to be disabled, then only power-down sequence steps 1, 2, 3 will be performed. (PRCM will clock gate clocks to the module, if all modules sharing that clock are disabled).

The Always ON power domain can not be switched to OFF, as it has many modules, not just EMAC0/1.

Regards,
Pavel

Asaf,

asaf hakun70 said:

But the modules are not on standby(STBYST = 0).

and the functional clocks are active(CLKACTIVITY_ETHERNET_GCLK = 1, CLKACTIVITY_RFT_GCLK = 1)

Even that these values are not what we expect, I see that the EMAC0/1 modules clocks are gated as I can not access (read/write) the EMAC0/1 registers after I perform the power down sequence:

TI8168_EVM#md 0x4A100000   -----> here I read the EMAC0 registers successful
4a100000: 4ec0020e 00000000 00000000 00000000    ...N............
4a100010: 00000000 00000000 00000000 00000000    ................
4a100020: 00000000 00000000 00000000 00000000    ................
4a100030: 00000000 00000000 00000000 00000000    ................
4a100040: 00000000 00000000 00000000 00000000    ................
4a100050: 00000000 00000000 00000000 00000000    ................
4a100060: 00000000 00000000 00000000 00000000    ................
4a100070: 00000000 00000000 00000000 00000000    ................
4a100080: 00000000 00000000 00000000 00000000    ................
4a100090: 00000000 00000000 00000000 00000000    ................
4a1000a0: 0000ff00 00000000 00000000 00000000    ................
4a1000b0: 00000000 00000000 00000000 00000000    ................
4a1000c0: 00000000 00000000 00000000 00000000    ................
4a1000d0: 00000000 00000000 00000000 00000000    ................
4a1000e0: 00000000 00000000 00000000 00000000    ................
4a1000f0: 00000000 00000000 00000000 00000000    ................
TI8168_EVM#md 0x4A120000   -----> here I read the EMAC1 registers successful
4a120000: 4ec0020e 00000000 00000000 00000000    ...N............
4a120010: 00000000 00000000 00000000 00000000    ................
4a120020: 00000000 00000000 00000000 00000000    ................
4a120030: 00000000 00000000 00000000 00000000    ................
4a120040: 00000000 00000000 00000000 00000000    ................
4a120050: 00000000 00000000 00000000 00000000    ................
4a120060: 00000000 00000000 00000000 00000000    ................
4a120070: 00000000 00000000 00000000 00000000    ................
4a120080: 00000000 00000000 00000000 00000000    ................
4a120090: 00000000 00000000 00000000 00000000    ................
4a1200a0: 0000ff00 00000000 00000000 00000000    ................
4a1200b0: 00000000 00000000 00000000 00000000    ................
4a1200c0: 00000000 00000000 00000000 00000000    ................
4a1200d0: 00000000 00000000 00000000 00000000    ................
4a1200e0: 00000000 00000000 00000000 00000000    ................
4a1200f0: 00000000 00000000 00000000 00000000    ................
TI8168_EVM#mw 0x481815D4 0x0 ---> start of power down sequence
TI8168_EVM#mw 0x481815D8 0x0
TI8168_EVM#mw 0x48181404 0x1
TI8168_EVM#md 0x4A100000   -----> here I can not read the EMAC0 registers
4a100000:

Hi Pavel,

Sorry if I wasn't clear, we would like to disbble the module and gate the clocks to the emac module.(i know it cannot be powered down).

Emac module has a seperate clock domain(ETHERNET_GCLK) inside the ALWAYSON power domain, I would like to insert it into forced sleep, so the clocks it supplies to the module will be gated.

BTW, I succedded in doing it to other modulse under ALWAYSON power domain, in ALWON_L3_SLOW_GCLK clock domain(such as spi, mcasp, etc...).

Regarding the Uboot output you sent, if I'm trying to do the same actions as you did I get the same results.

But I'm writing to the registers from application mode(not from uboot) using mmap(it worked for other modules it should work here also), and I get the results I sent - it is possible to read the registers after the writing actions, and according to their values clocks to the module are still active.

Regards,

Asaf

Asaf,

See also the below wiki pages:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_SUSPEND_RESUME_User_Guide

Power Domains - All switchable(on board power switch) Power domains are switched off.(if "turnoff_idle_powerdomains" enabled) ALWON remains on.

Peripherals - All peripherals in ALWON domain remain on as they dont have power switches.

http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_Power_Estimation

The calculations in the power spreadsheet assumes that with exception of Always-on power domain, the rest of power domains are switched off when all the modules corresponding to that power domain are not used.

BR
Pavel

Pavel,

Please read my previous reply.

"Sorry if I wasn't clear, we would like to disbble the module and gate the clocks to the emac module.(i know it cannot be powered down)"

Why inserting to stanby and clock gating is not working properly??

Regards,

Asaf

Asaf,

asaf hakun70 said:

Please read my previous reply.

"Sorry if I wasn't clear, we would like to disbble the module and gate the clocks to the emac module.(i know it cannot be powered down)"

Sorry, I post this answer before reading your replay.

asaf hakun70 said:

Why inserting to stanby and clock gating is not working properly??

I think it is working properly. I tried this also from user space (after u-boot, linux kernel and rootfs are loaded and up).

root@dm816x-evm:~# devmem2  0x4A120000  -----> here I read the EMAC1 register successful
/dev/mem opened.
Memory mapped at address 0x4034b000.
Read at address  0x4A120000 (0x4034b000): 0x4EC0020E
root@dm816x-evm:~# devmem2  0x481815D8 w 0x0 ---> gate EMAC1 clock
/dev/mem opened.
Memory mapped at address 0x4025f000.
Read at address  0x481815D8 (0x4025f5d8): 0x00000002
Write at address 0x481815D8 (0x4025f5d8): 0x00000000, readback 0x00000000
root@dm816x-evm:~# devmem2  0x481815D8
/dev/mem opened.
Memory mapped at address 0x40233000.
Read at address  0x481815D8 (0x402335d8): 0x00030000  ----> [17:16] IDLEST = 0x3
root@dm816x-evm:~# devmem2 0x48181404 w 0x1  ---> switch to SW_SLEEP
/dev/mem opened.
Memory mapped at address 0x402a2000.
Read at address  0x48181404 (0x402a2404): 0x00000302
Write at address 0x48181404 (0x402a2404): 0x00000001, readback 0x00000001
root@dm816x-evm:~# devmem2 0x4A120000  -----> here I can not read the EMAC1 register
/dev/mem opened.Unhandled fault: Precise External Abort on non-linefetch (0x1018) at 0x402ae000

Memory mapped at address 0x402ae000.
Bus error
root@dm816x-evm:~#

Note also that when we set CM_ALWON_ETHERNET_1_CLKCTRL[1:0] MODULEMODE to 0x0 (disable module), the [17:16] IDLEST read-only bits are set to 0x3 (Module is disabled and cannot be accessed).

Regards,
Pavel

Hi Pavel,

My questions marked in red.

root@dm816x-evm:~# devmem2  0x4A120000  -----> here I read the EMAC1 register successful

/dev/mem opened.
Memory mapped at address 0x4034b000.
Read at address  0x4A120000 (0x4034b000): 0x4EC0020E
root@dm816x-evm:~# devmem2  0x481815D8 w 0x0 ---> gate EMAC1 clock
/dev/mem opened.
Memory mapped at address 0x4025f000.
Read at address  0x481815D8 (0x4025f5d8): 0x00000002
Write at address 0x481815D8 (0x4025f5d8): 0x00000000, readback 0x00000000
root@dm816x-evm:~# devmem2  0x481815D8
/dev/mem opened.
Memory mapped at address 0x40233000.
Read at address  0x481815D8 (0x402335d8): 0x00030000  ----> [17:16] IDLEST = 0x3->>what about standby bit(18), why isn't it turned on also? you got zero there that means the module is still functional.
root@dm816x-evm:~# devmem2 0x48181404 w 0x1  ---> switch to SW_SLEEP
/dev/mem opened.
Memory mapped at address 0x402a2000.
Read at address  0x48181404 (0x402a2404): 0x00000302
Write at address 0x48181404 (0x402a2404): 0x00000001, readback 0x00000001
root@dm816x-evm:~# devmem2 0x4A120000  -----> here I can not read the EMAC1 register
/dev/mem opened.Unhandled fault: Precise External Abort on non-linefetch (0x1018) at 0x402ae000

Memory mapped at address 0x402ae000.
Bus error
root@dm816x-evm:~# 

please try to read 0x48181404 in the end of all your actions, I'm getting 0x00000301(which means clocks are still active).

Regards,

Asaf

Asaf,

asaf hakun70 said:

Read at address  0x481815D8 (0x402335d8): 0x00030000  ----> [17:16] IDLEST = 0x3->>what about standby bit(18), why isn't it turned on also? you got zero there that means the module is still functional.

Even that bit 18 is 0x0, the EMAC1 module is not functional. The read test shows that.

asaf hakun70 said:

please try to read 0x48181404 in the end of all your actions, I'm getting 0x00000301(which means clocks are still active).

Evan that bit [8] and [9] are 0x1, the clocks are not active. The read test shows that.

Regards,
Pavel

Hi Pavel,

If the clocks are not active why according to the TRM they are active?

And why according to the registers values the module appear to be functional and not in standby?

Regards,

Asaf