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DM8168 as pcie end point. Question about memory map.

Oleg Koksharov
Prodigy 100 points

Hello.

I want to map inbound pcie address to Address Space One. I allocate 4kBytes for RC in BAR2. In my driver, i use pcie application registers IB_BAR0, IB_START0_LO,IB_START_HI, IB_OFFSET for address translation. So i write in IB_BAR0 = 0x2, in IB_START0_LO = 0x88200000(Base address from RC is 0x88200000), IB_START0_HI = 0 and in IB_OFFSET0 = 0x20000000 (the start address in my memory).

So, when i try to read memory from linux with devmem2 0x20000000, i get the bus error like that:

/dev/mem opened.Unhandled fault: external abort on non-linefetch (0x1018) at 0x400dc000

Memory mapped at address 0x400dc000.
Bus error

But when i map pcie address to OCMC0,1 or DDR, all okey.

So, my first question. Can i map inbound pcie address in PCIe gen memory(0x20000000-0x2FFFFFFF)? And second. If yes, how to do that?

  • 0
    TI__Guru**** 170625 points
    Hi Oleg,

    I can provide you the below pointers:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Driver_User_Guide - mmap()
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Boot_Driver_User_Guide
    http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#How_can_I_set_up_BAR_sizes.3F
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_U-Boot_PCIe_Boot_User_Guide#BAR_addressing_mode_and_BAR_sizes

    http://e2e.ti.com/support/embedded/linux/f/354/t/162993
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/136108
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/200969
    http://e2e.ti.com/support/embedded/linux/f/354/t/200968

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 100 points
    Thank you, Pavel.

    But all links from forum, about using PCIe controller as Root Complex. I use it as end point.
    I read all this links in wiki, and there is no answer for my question.

    My question, can i map Inbound pcie address to PCIe Gen memory pool(physically), or it used only for outbound transfers, or only in RC mode.
    Because i confused by this quote in Davinci TRM:

    17.2.4.2 Address Space One
    The second address space/region is used for data transfer. The BAR values setup within the PCIe Local
    Configuration Registers define where within the memory map of the CPU on Root Complex side are the
    End Points located. All locations other than what is setup in BAR registers of the End Points are on the
    Root Complex side.
    The Address Space One is mapped to multiple devices in RC mode. Each remote device could be
    allocated a portion of this memory space and any transaction that is targeted to this address space gets
    converted to a PCIe transaction targeted to the appropriate remote PCIe device.

    But in this TRM also written this about inbound address translation:

    However, Address Translation for Address Space One requires the use of one of the four Regions
    (Regions[0-3]) to map accepted TLPs to Internal/Physical memory address. Four region specific memory
    mapped registers exist and used by the Inbound Address Translator.
  • 0 in reply to Oleg Koksharov
    TI__Genius 15605 points
    See the "PCIe Gen2" row Table 5-1. L3 Master/Slave Connectivity in the datasheet. The Xs in this row show where the inbound transactions can land. Why are you trying to map inbound transactions to 0x20000000?
  • 0 in reply to B.C.
    Prodigy 100 points
    Thank you very much.