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Pin used by Rom Code in DM8168

Massimiliano Cialdi
Expert 1995 points

Hi,

I use DM8168, and I want to boot from SPI NOR.

In the reference manual I find (25.7.5.4 Pins Used):

"Note that all the pins might not be driven at boot time. The default state of the other SPI chip
select pins could be low at POR, so care must be taken if any other devices are connected to CS[1],
CS[2], or CS[3]. External logic must be used to ensure that the chip select to these devices are not
enabled by default."

So I chose pin GP0[25] with external pull up to drive the external logic based on OR gate. I chose GP0[25] because in the reference manual this pin is declared to be wuth pull disabled and with only one function muxed (PINCTRL200).

Unfortunately this pin seems to be driven low immediately after reset (maybe by rom code?), but this does not match with what is written in reference manual.

Other pins available in my project are:

GP0[23]

GP0[24]

GP0[26]

GP0[31]

GP1[12]

GP1[11]


I need a signal that is driven high, or pulled up or unreferenced after reset. Which of these meets these requirements?

best regards Max

  • 0
    TI__Guru**** 170625 points
    Hi Mastupristi,

    GP0[25] is stated as DRIVE: H / L (section 4.2.4 of DM816x datasheet SPRS614E), which means the driving state of the pin after PORn is Low.

    GP0[26] is stated as DRIVE: L / H, which means the driving state of the pin after PORn is High.

    See also how DM816x EVM is designed, it has SPI boot mode.

    BR
    Pavel
  • 0 in reply to Pavel Botev
    Expert 1995 points

    I'm confused.

    in Reference manual, Table 1-247, PINCTRL200 (that controls GP0[25]) is stated that the default value is PULL DOWN SELECTED, and PULL are disabled.

    best regards

    max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 170625 points

    mastupristi said:
    in Reference manual, Table 1-247, PINCTRL200 (that controls GP0[25]) is stated that the default value is PULL DOWN SELECTED, and PULL are disabled.

    The same is stated in datasheet, Table 5-9 PINCTRL200 But this is valid after PORn (pull disable, signal is low). During PORn we have internal pull up selected and signal is high. See Table 4-5 GP0[25], table note (2)

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 1995 points

    But table 1-247 in ref man doesn't refer at pin state during POR, it refers to the default state of the pin.

    therefore, if rom code doesn't drive GP0[25], I'm expecting that GP0[25] is not pulled up nor down, so the pin should be driven high by my pull up.

    Furthermore it seems to me there is mismatch in table 4-5 and 1-247 describing PINCTRL200

    best regards

    max