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DM8168 Codec Engine Caching

fabio ortolano
Intellectual 330 points

Hello

we are investigating on enabling cache on DM8168 DSP. We are running the "universal_copy" example in codec engine togheter with capture_encode OMX example. We get the buffer from capture component, pass the pointer to DSP and encode the result (a simple copy). We add these lines to the "all_syslink.cfg" (in ti-ezsdk_dm816x-evm_5_05_02_00/component-sources/codec_engine_3_22_01_06/examples/ti/sdo/ce/examples/servers/all_codecs).

if (myName == "DSP") {
    var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    var obj = new Cache.Size;
    obj.l1pSize = Cache.L1Size_32K;
    obj.l1dSize = Cache.L1Size_32K;
    obj.l2Size = Cache.L2Size_128K;
    Cache.initSize = obj;  
    Cache.MAR128_159 = 0xFFFFFFFF;
    Cache.MAR160_191 = 0xFFFFFFFF;
    Cache.MAR192_223 = 0xFFFFFFFF;
    Cache.MAR224_255 = 0xFFFFFFFF;
}

We want to enable caching of the buffers allocated in SharedRegion2 on DSP. Enabling th caching we don't see any improvements, even if we use the universal copy alg in "release" mode using 

xdc.loadPackage('ti.sdo.ce.examples.codecs.' + 'universal_copy.UNIVERSAL_COPY').profile = 'release';


What do we need to enable Cache on DSP for Shared Region 2 buffers? We found also that using CCS6 and Memory Browser, the buffers are not painted with the colors of L2 Cache

  • 0 in reply to Margarita Gashova
    Intellectual 330 points
    Hello Margarita, we read the post and verified that the our configuration is corret. The problem seems to be this line:

    obj.l2Size = Cache.L2Size_128K;

    If I try to configure the L2 cache (half size), I found with the emulator that only the L1 works. I think that L2 is configured in the bios module like a standard memory (IRAM). My configuration seems to be overwritten by bios. Actually the internal memory is configured like IRAM and not half IRAM and half cache. How we could configure IRAM from server cfg file? What module i have to load? Thanks
  • 0 in reply to fabio ortolano
    TI__Guru* 80190 points

    Hello,

    Unfortunately, I am not an expert in this area.
    I would recommend you to check the TRM (C674x DSP Subsystem) also.

    You could try to post in :



    BR
    Margarita

  • 0 in reply to Margarita Gashova
    Intellectual 330 points

    Hello Margarita, during the night we solve the mistery. The solution is that the server of the codec engine loads standard platform from xdc package

    ti-ezsdk_dm816x-evm_5_05_02_00/component-sources/xdctools_3_23_03_53/packages/ti/platforms/evmDM8168

    In this file are defined a lot of things and the configuration for the cache. The platform is than re-configured in the server of the Codec Engine. In detail, you can see the file "serverplatform.xs" in ti-ezsdk_dm816x-evm_5_05_02_00/component-sources/codec_engine_3_22_01_06/examples/ti/sdo/ce/examples/servers/all_codecs

    /* platform instances used by this package */
Build.platformTable["ti.platforms.evmTI816X:DSP"] = {
    externalMemoryMap: [
        [ "DDR3_DSP",   TI816X_DSP_ExtMemMap.DDR3_DSP ],
        [ "DDRALGHEAP", TI816X_DSP_ExtMemMap.DDRALGHEAP ],
        [ "DDR3_SR1",   TI816X_DSP_ExtMemMap.DDR3_SR1 ],
        [ "DDR3_SR0",   TI816X_DSP_ExtMemMap.DDR3_SR0 ]
    ],
    codeMemory: "DDR3_DSP",
    dataMemory: "DDR3_DSP",
    stackMemory: "DDR3_DSP",


    l2Mode : "128k"
};

    In this way you enable the L2 Cache and conseguently reduce the IRAM. You can verify this on the .map file of the server generated after the compile stage in "package" directory. You can also verify this using CCS and the "Cache" view.