• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 101 subscribers
  • Views 617 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM648 BIOS Cache Configuration Problem...

JRasmussen
Intellectual 720 points

Hello,

 We are using a DM648 (the EVM currently), and in setting up DSP BIOS' configuration, we see that we can't specify more than 256k for the L2 Cache, even though the DM648 has 512k of L2 Cache space. Does anyone know of a workaround to let us set the cache size to 512k?

 

Also, isn't there a TI DSP Bios maillist that non-TIers can join?

 Thanks,

--James Rasmussen

 

  • 0
    TI__Mastermind 41665 points

    The DM648, as well as most any other C64x+ device, only supports up to 256k of L2 as cache, so although the DM648 actually has 512k of L2 SRAM, only 256k can be allocated to cache, the rest will just be regular addressable SRAM. The possible cache configurations are discussed in section 2.3.3 of SPRUE6 available below, the actual registers you configure for L2 are shown in section 4.4 of SPRU871 available below.

    http://focus.ti.com/lit/ug/sprueu6/sprueu6.pdf

    http://focus.ti.com/lit/ug/spru871i/spru871i.pdf

  • 0 in reply to Bernie Thompson TI
    Intellectual 720 points

     Thanks for the response.

     Let me point you to http://focus.ti.com/lit/er/sprz263c/sprz263c.pdf.  In the Advisory 1.1.5 section which explains a caution as to sharing code and Cache in the L2 Cache area of memory (The DSP Gem cores seem to have this problem).

    In our case, there is no problem with us running our application in DDR2 Ram, and we really could use the full 512kb of RAM for Cache.  I know the TNETV2865 Bios Platform was fixed to allow more cache memory to be specified, so I was wondering what it would take to get the DSP Bios platform files fixed for the DM648?

     Thanks,

    --James Rasmussen

     

  • 0 in reply to JRasmussen
    TI__Mastermind 41665 points

    I agree that advisory 1.1.5 is problematic and that similar issues are found on other C64x+ based devices, however this does not mean that the DM648 in particular supports using all L2 memory as cache.

     The TNETV parts are not widely available, essentially they are not mass market devices, even if a non mass market part like the TNETV you mention has a C64x+ with larger cache capacity, it does not mean that the DM648 supports this feature. Because the DM648 does not support this feature the BIOS platform files will not support this feature. You could manually setup registers however you want, however since there is no setting for a 512k cache in the current DM648 documentation (if you can find this please let me know) you would be setting reserved values which is not suggested or supported by TI.