According to the Section 10.11.2 of the OMAP-L138 Reference Guide (SPRUGM7E), in order to operate the device in RTC-only power-down mode, some type of external hardware logic is required to disconnect the CKE output and to drive this pin low in order to keep the DD2 memory in self-refesh mode. Here is the exact phrasing from the manmual:
"After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is needed to disconnect the CKE output pin from the memory and to drive the memory's CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the TMS320C674x/OMAP-L1x Processor DDR2/mDDR Memory Controller User's Guide (SPRUGJ4)."
I have reviewed the Memory Controller User's Guide and cannot find any mention of requiring external logic in order to place the DDR2 memory into self-refresh mode and then power down the DDR2 memory controller. Furthermore, Table 2-10 in Section 2.8.6 of the OMAP-L138 data sheet document indicates that all the I/O associated with the DDR2 Memory Controller is configured with internal pull-down resistors (PULL = IPD). This alone should ensure that the DDR_CKE output remains low if not being driven high by the controller. These pull-downs are permanent and not impacted by either the PUPD_ENA or PUPD_SEL system configuration (SYSCFG) registers. So the question is simple, do I need to add any external components to support sustaining the DDR2 memory in self-refesh if the DDR memory controller is placed in low power mode?
