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SPI Clock and Data lines routing / distribution to multiple slaves

Jeremy Huffman
Prodigy 80 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138, CDCLVC1112

I am using an OMAP-L138 C6000 and one of its SPI bus channels.

My questions are mainly concerning with the electrical propagation and routing of the SPI Clock and data signals.

Please answer the questions bearing in mind my application will have up to 50 slaves to this single SPI channel.  Likely the PCB will be split into three with flex cables and distance from the OMAP to the end slave should not exceed 3 inches.

 Here are my questions:

1)  What is the most optimal clock distribution circuitry recommended in order to ensure that the clock has the proper power level and signal integrity at the receiving slave ICs.?  Do I need a multiple output clock distribution chip to be able to handle the total number of slaves (~50)? 

2)  Repeat question #1, but with respect to the SPI data lines -- need I distribute these?

3)  Which routing topolog(ies) would be the most optimal to use in my application -- star, daisy chain, etc?

4)  Are there any application notes or white papers that I could reference to support this effort?

Thanks in advance for any support!

Regards,
Jeremy

  • 0
    TI__Expert 4760 points

    Hi Jeremy ,

    Welcome to E2E

    Can you please explain me the connectivity scheme for the 50 slave device, just be curious we don’t have that many chip select lines available in OMAP-L138

    Regards

    Antony

  • 0
    TI__Mastermind 35645 points

    Hi Jeremy,

    Thanks for your post.

    I think, you need to explore for different options to try out to modify the timing of its generation of the available chip select signal, so that, the SPI can support the timing requirements of various slave devices. This would help the CPU decide to generate the appropriate delays automatically, thereby, this would avoid additional overhead to the CPU.

    For more understanding on SPI master and slave mode settings, please refer sections 30.2.5 & 30.2.6 in the omapl138 TRM as below:

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    Also, there is an application report for understanding PCB routing rule specifications as below:

    http://www.ti.com/lit/an/spraav0a/spraav0a.pdf

    The above doc. would help you in designing the PCB for a high-speed peripheral which involves designing the preliminary bus topologies/stackup and evaluate the simulations for signal integrity and timings.

    Thanks & regards,
    Sivaraj K

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  • 0 in reply to Antony Samsunil
    Prodigy 80 points

    Antony,

    As far as the chip select to all 50 devices you are right there is a limitation on the available GPIO, especially in my particular system so in this case I will most likely use the appropriate decoders to minimize my GPIO load on the OMAP.

    The SPI routing scheme will be the typical SPI bus format with all slaves being independent.  

    I appreciate your interest and look forward to any suggestions that you may have.

    Regards,

    Jeremy

  • 0 in reply to Jeremy Huffman
    TI__Mastermind 46460 points

    Connecting 50 devices to a single SPI master will require considerable design.  There are multiple issues to overcome.  The 3 most significant are delay, reflections on the clock signal and drive strength.  All of these must be resolved for each output driver and each load.

    1. You need to use a star configuration for the clock.  50 loads will require multiple levels of buffering.  You need to use large fan-out buffers.  for SPI, I recommend a separate driver for each clock load.  Each of the outputs should have a series termination built into the output.  You mentioned that some of the loads will be over cables.  Cables have high capacitance and may have additional impairments from the connectors.  A snubber temination will probably be needed after the cable.  If the connected board again has multiple loads, another fan-out buffer will be needed there.  Example clock buffers are CDCLVC1112 or CVCDF2310 and similar from TI.
    2. Data could be routed as a daisy-chain.  However, the individual SPI data buffers cannot drive the capacitance or even the leakage of 50 inputs.  This will also need to be broken into buffered sections.  You can use automatic bi-directional buffers from the TXS0108B or TSB0108 families.
    3. Delay through all of the buffers and the signal routing will limit the maximum clock speed.  This will need to be managed carefully for the product to operate reliably in production.  Similarly, variations in the clock and data buffer topologies will affect the maximum clock rate.

    This is a unique requirement.  Careful design can yield a robust implementation.  Clock reflections from branched routing are the primary causes of multiple-slave SPI implementations.  Proper buffering and terminations are a must.

    Tom

     

  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 80 points

    Thanks Sivaraj, the first reference is helpful in better understanding the nature of the SPI Bus and how I can adjust it to compensate for the buffer/routing delays between the master and slave.  The second reference is a good signal integrity reference to review.

    Regards,
    Jeremy

  • 0 in reply to Tom Johnson 16214
    Prodigy 80 points

    Thanks, Tom.  I appreciate your detailed feedback and suggestions!

    Let me follow up to each of your points:

    1.  I am looking at using clock buffers and trying to minimize the propagation delay.  Would zero delay buffers be acceptable to use?

    2.  May I use the same clock fanout buffers to process the MOSI?  As for the MISO, I am considering using hex buffers with tri-state outputs (connecting all these outputs together and routing to the DSP).

    3.  I will focus on managing this delay and try to keep the trace lengths as matched as possible.

    Jeremy

  • 0 in reply to Jeremy Huffman
    TI__Mastermind 46460 points

    Jeremy,

    1.  No, you do not need zero-delay buffers.  They contain PLLs and have a long start-up time.  This may cause problems at start-up.

    2.  You do not need clock fan-out buffers for MOSI.  Since MOSI does not latch signals by its edge, the signal integrity requirements are much lower.  The data just needs to be stable when it is sampled.  Therefore, multiple loads can be attached to a single output.  You could use clock buffers with multiple loads on each output but this is not a requirement.

    I do not understand your idea for MISO.  Would you enable the 3-state buffer outputs individually through something like GPIO control?  This still might be pretty complicated.

    3.  OK

    Is there such a device as an SPI expander?  Perhaps using a device of this type would be much simpler.  clock buffering and proper routing and termination would still be needed for each segment.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 10 points
    Do you recommend using clock buffers for SPI applications where there is up to 8 devices (SS0-7) and where the controller (clock driver) is on one board and the SPI Devices are on closely connected sub-boards. If so what device do you recommend and is there a device where output drive can be adjusted 4,8,16... ma to optimize for signal integrity simulations.
  • 0 in reply to Gregory Andre99
    TI__Mastermind 46460 points

    Gregory,

    Similar to the previous discussion, it depends on clock speed and routing topology.  Clock buffers may be needed when connecting to as few as 2 slaves if the clock speed is fast or if the electrical lengths of the routed clocks are long enough to produce reflections that result in loss of monotonicity of the clock signal through the active transition period.  Clock buffer drive strength can be managed by insertion of series resistance at the output.  Also, signals over cables or connectors to a 2nd board will encounter significant inductance and capacitance.  Proper termination will be needed to maintain clock signal integrity.

    Tom