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Boot Sequence stuck on Waiting for SFT on AM1808

Taqi Mustafa
Intellectual 890 points
Other Parts Discussed in Thread: AM1808, OMAPL138

I am trying to bring up my AM1808 custom board, but when i try to erase the NAND flash, it stuck on "waiting for SFT". I have modified all the files i.e. Uboot image, AIS Image and SFH tool.

  • 0
    TI__Guru** 116100 points

    Hi,

    Are you testing this board for a first time?

    Have you initialized the DDR using gel script?

    Have you calculated the DDR timing values using the spread sheet provided in the wiki links?

    http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 890 points

    Are you testing this board for a first time?

    It is the similar board with the DDR2 Replaced by a new one, So yes i am testing this board for the 1st time.

    Have you initialized the DDR using gel script?

    I don't have the jTag with me now. But i can test it if you tell me the steps how to initialize the DDR. Am i just suppose to Load the GEL files in the board ?

    Have you calculated the DDR timing values using the spread sheet provided in the wiki links?

    Yes, i have calculated the DDR timing accordingly to the RAM specification attached on the board

  • 0 in reply to Taqi Mustafa
    TI__Guru** 116100 points

    Hi,

    You can use gel file for your AM1808 board from the following path.

    <CCS installation>/ccsv5/ccs_base/emulation/boards/evmomapl138/gel/EVMOMAPL138_ARM.gel.

    You have to change the DDR registers as per your attached DDR on your board.

    Are you using DDR or mDDR?

    Please go through the DEVICE_DDRConfig function to understand how to change the DDR register vaules.

    Ex:

          EMIFDDR_SDTIMR1 = (0x7F << 25)             |  // tRFC
                            (0x07 << 22)             |  // tRP
                            (0x07 << 19)             |  // tRCD
                            (0x07 << 16)             |  // tWR
                            (0x1F << 11)             |  // tRAS
                            (0x1F << 6)              |  // tRC
                            (0x07 << 3)              |  // tRRD
                            (EMIFDDR_SDTIMR1 & 0x4)  |  // Reserved
                            (0x03 << 0);                // tWTR

    0x07 is the value at offset 22 of STIMR1 register of DDR.

    Please refer the OMAPL138 TRM chapter 14.4.5.

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 890 points

    i have initialize the DDR script using CCS4.

    ARM9_0: Output:     Memory Map Cleared.
    ARM9_0: Output:     ---------------------------------------------
    ARM9_0: Output:     Memory Map Setup Complete.
    ARM9_0: Output:     ---------------------------------------------
    ARM9_0: Output:     PSC Enable Complete.
    ARM9_0: Output:     ---------------------------------------------
    ARM9_0: The GEL callback "OnTargetConnect()" is no longer running atomically
    ARM9_0: Output:     PLL0 init done for Core:300MHz, EMIFA:25MHz
    ARM9_0: Output:     mDDR initialization is in progress....
    ARM9_0: Output:     PLL1 init done for DDR:150MHz
    ARM9_0: Output:     Using mDDR settings
    ARM9_0: Output:     mDDR init for 150 MHz is done
    ARM9_0: Output:     ---------------------------------------------
    ARM9_0: Output:     DSP Wake Complete.
    ARM9_0: Output:     ---------------------------------------------