DSP Core slow down?

Hi Remco,

I'm copying code from an ugly but working project to a new project to improve its structure and maintainability.

I'm suspecting on your latest code changes.

Also it depends on what  portion of code you have changed.

Hi,

I've only restructured code, not modified it. I've created sub-functions to make logical blocks and have moved code around files. As far as the DSP is concerned the code should be identical.

So I've no idea where to start looking for clues.

Do you perhaps have options for what influences the execution speed of the core? I've checked the PLL and clock and they are the same.

Thanks in advance.

Kind regards,

Remco Poelstra

Hi Remco,

How does cycle count is giving problem to your code?

I am not exactly clear what you are trying to say/whats your aim/problem?

Hi,

The problem was caused by the confusing reset behaviour of the dsp. By the time I started measuring, the pll or clock configuration was reconfigured causing a slow core clock.

I worked around that by always doing a hardware reset of the dsp.

Regards,

Remco Poelstra

Hi, 

May be you are having corruption /bug in your code. 

How do you confirm that pll configuration is reconfigured.