AISgen settings for OMAP L138

Andrey Bondarev

Prodigy 170 points

Other Parts Discussed in Thread: OMAPL138

We using TI AISgen tool for creating images for the processor (OMAPL138).

When we load image onto the processor and run it – sometimes we experiencing “crash” of the our device.

But when we load program via J-Tag – crushes do not happen. We are using IAR IDE for ARM code development.

During our system start up we rely on IAR 2475.omap_with_ddr_456MHz.cfg

7774.omapl138_ddr_456MHz.txt

// -----------------------------------------------------------------------
// This file contains the DDRRAM set up configuration for the TMS470R1B768.
//
//
// Revision : 0.01 JM 2/16/06
//
//-------------------------------------------------------------------------

CHGBIT (addr, mask, data)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg &= ~mask;
	reg |=  data;
  __writeMemory32(reg, addr, "Memory");
}

CLRBIT (addr, mask)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg &= ~mask;
  __writeMemory32(reg, addr, "Memory");
}

SETBIT (addr, mask)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg |= mask;
  __writeMemory32(reg, addr, "Memory");
}

TESTBIT (addr, mask)
{
	return(__readMemory32(addr, "Memory") & mask);
}

lpsc0Enable(in_domain, in_module, in_next_state)
{
__var psc_base;
__var reg;
__var module_offest;

  psc_base  = 0x01C10000;
  module_offest = in_module << 2;

  // spin until existing transitions are done.
  while(TESTBIT(psc_base + 0x0128,in_domain));
	
	// if we are already in the requested state...just return.
	if(in_next_state != TESTBIT(psc_base + 0x0800 + module_offest, 0x3F))	// !PSC_ENABLE
	{
		// setup the transition...clear the bits before setting the next state.
		CHGBIT(psc_base + 0x0A00 + module_offest,0x3F,in_next_state); // MDCTRL + module_offest
	
	  // kick off the transition.
	  SETBIT(psc_base + 0x0120,in_domain); // PTCMD
	
	  // spin until transition is done.
	  while(TESTBIT(psc_base + 0x0128,in_domain));
		
		//reg = TESTBIT(psc_base + 0x0800 + module_offest, 0x3F);
   	//__message "PSC 0 Module: ", in_module:%d,", MDSTAT: ", reg:%x, "\n";
   	
	  while(in_next_state != TESTBIT(psc_base + 0x0800 + module_offest, 0x3F));
	}
}

lpsc1Enable(in_domain, in_module, in_next_state)
{
__var psc_base;
__var reg;
__var module_offest;

  psc_base  = 0x01E27000;
  module_offest = in_module << 2;

  // spin until existing transitions are done.
  while(TESTBIT(psc_base + 0x0128,in_domain));
	
	// if we are already in the requested state...just return.
	if(in_next_state != TESTBIT(psc_base + 0x0800 + module_offest, 0x3F))	// !PSC_ENABLE
	{
		// setup the transition...clear the bits before setting the next state.
		CHGBIT(psc_base + 0x0A00 + module_offest,0x3F,in_next_state); // MDCTRL + module_offest
	
	  // kick off the transition.
	  SETBIT(psc_base + 0x0120,in_domain); // PTCMD
	
	  // spin until transition is done.
	  while(TESTBIT(psc_base + 0x0128,in_domain));
		
		//reg = TESTBIT(psc_base + 0x0800 + module_offest, 0x3F);
   	//__message "PSC 1 Module: ", in_module:%d,", MDSTAT: ", reg:%x, "\n";
   	
	  while(in_next_state != TESTBIT(psc_base + 0x0800 + module_offest, 0x3F));
	}
}

SetupPLL0()
{
__var i;
	// unlock the system config registers.
	__writeMemory32(0x83E70B13, 0x01C14038, "Memory"); // SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
	__writeMemory32(0x95A4F1E0, 0x01C1403C, "Memory"); // SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;

  // unlock pll regs.
  CLRBIT(0x01C1417C, 0x00000010); // CLRBIT(SYSCONFIG->CFGCHIP[0], PLL0_MASTER_LOCK);

  // prepare to enable pll (PLLENSRC must be clear for PLLEN to have effect).
  CLRBIT(0x01C11100, 0x00000020); // CLRBIT(PLL0->PLLCTL, PLLENSRC);

  // disable external clock source.
  CLRBIT(0x01C11100, 0x00000200); // CLRBIT(PLL0->PLLCTL, EXTCLKSRC);

  // switch to bypass mode...wait 4 cycles to ensure it switches properly.
  CLRBIT(0x01C11100, 0x00000001); // CLRBIT(PLL0->PLLCTL, PLLEN);
  for (i = 0; i < 4; i++) {}

  // select clock mode (on-chip oscillator or external).
	CLRBIT(0x01C11100, 0x00000100); // CLRBIT(PLL0->PLLCTL, CLKMODE);
	SETBIT(0x01C11100, 0x00000000); // SETBIT(PLL0->PLLCTL, (clkmode << CLKMODE_SHIFT));

  // reset the pll.
  CLRBIT(0x01C11100, 0x00000008); // CLRBIT(PLL0->PLLCTL, PLLRST);

  // disable the pll...set disable bit.
  SETBIT(0x01C11100, 0x00000010); // SETBIT(PLL0->PLLCTL, PLLDIS);

  // PLL initialization sequence
  //----------------------------
  // power up the pll...clear power down bit.
  CLRBIT(0x01C11100, 0x00000002); // CLRBIT(PLL0->PLLCTL, PLLPWRDN);

  // enable the pll...clear disable bit.
  CLRBIT(0x01C11100, 0x00000010); // CLRBIT(PLL0->PLLCTL, PLLDIS);

  /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
  __delay(10);

  // program the required multiplier value.
  __writeMemory32(18, 0x01C11110, "Memory"); // PLL0->PLLM = pllm; 	// with postdiv  = 1

  // program postdiv ratio.
  __writeMemory32(0x00008000 | 0, 0x01C11128, "Memory"); // PLL0->POSTDIV = DIV_ENABLE | postdiv (0 + 1 = 1);

  // spin until all transitions are complete.
  while (TESTBIT(0x01C1113C, 0x00000001)) {} // while (CHKBIT(PLL0->PLLSTAT, GOSTAT)) {}

  // program the divisors.
  __writeMemory32(0x00008000 | 0, 0x01C11118, "Memory"); // PLL0->PLLDIV1 = DIV_ENABLE | plldiv1;
  __writeMemory32(0x00008000 | 1, 0x01C1111C, "Memory"); // PLL0->PLLDIV2 = DIV_ENABLE | plldiv2;
  __writeMemory32(0x00008000 |11, 0x01C11120, "Memory"); // PLL0->PLLDIV3 = DIV_ENABLE | plldiv3;
  __writeMemory32(0x00008000 | (((0+1)*4)-1), 0x01C11160, "Memory"); // PLL0->PLLDIV4 = DIV_ENABLE | (((plldiv1 + 1) * 4) - 1);
  __writeMemory32(0x00008000 | 0, 0x01C11168, "Memory"); // PLL0->PLLDIV6 = DIV_ENABLE | plldiv1;
  __writeMemory32(0x00008000 | 9, 0x01C1116C, "Memory"); // PLL0->PLLDIV7 = DIV_ENABLE | plldiv7;

  // kick off the transitions and spin until they are complete.
  SETBIT(0x01C11138, 0x00000001); // SETBIT(PLL0->PLLCMD, GOSET);
  while (TESTBIT(0x01C1113C, 0x00000001)) {} // while (CHKBIT(PLL0->PLLSTAT, GOSTAT)) {}

  /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
  __delay(10);   /*128 MXI Cycles*/

  // bring pll out of reset and wait for pll to lock.
  SETBIT(0x01C11100, 0x00000008); // SETBIT(PLL0->PLLCTL, PLLRST);
  __delay(10);

  // exit bypass mode.
  SETBIT(0x01C11100, 0x00000001); // SETBIT(PLL0->PLLCTL, PLLEN);

  // lock pll regs.
  SETBIT(0x01C1417C, 0x00000010); // SETBIT(SYSCONFIG->CFGCHIP[0], PLL0_MASTER_LOCK);
	
}

SetupPLL1()
{
__var i;
	// unlock the system config registers.
	__writeMemory32(0x83E70B13, 0x01C14038, "Memory"); // SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
	__writeMemory32(0x95A4F1E0, 0x01C1403C, "Memory"); // SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;


   // unlock pll regs.
   CLRBIT(0x01C14188, 0x00000020); // CLRBIT(SYSCONFIG->CFGCHIP[3], PLL1_MASTER_LOCK);

   // prepare to enable pll (PLLENSRC must be clear for PLLEN to have effect).
   CLRBIT(0x01E1A100, 0x00000020); // CLRBIT(PLL1->PLLCTL, PLLENSRC);
   CLRBIT(0x01E1A100, 0x00000200); // CLRBIT(PLL1->PLLCTL, EXTCLKSRC);

   // switch to bypass mode...wait 4 cycles to ensure it switches properly.
   CLRBIT(0x01E1A100, 0x00000001); // CLRBIT(PLL1->PLLCTL, PLLEN);
   for (i = 0; i < 4; i++) {}

   // reset the pll.
   CLRBIT(0x01E1A100, 0x00000008); // CLRBIT(PLL1->PLLCTL, PLLRST);

   // disable the pll...set disable bit.
   SETBIT(0x01E1A100, 0x00000010); // SETBIT(PLL1->PLLCTL, PLLDIS);

   // PLL initialization sequence
   //----------------------------
   // power up the pll...clear power down bit.
   CLRBIT(0x01E1A100, 0x00000002); // CLRBIT(PLL1->PLLCTL, PLLPWRDN);

   // enable the pll...clear disable bit.
   CLRBIT(0x01E1A100, 0x00000010); // CLRBIT(PLL1->PLLCTL, PLLDIS);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   __delay(10);

   // program the required multiplier value.
   __writeMemory32(18, 0x01E1A110, "Memory"); // PLL1->PLLM = pllm;	// postdiv = 1


   // program postdiv ratio.
   __writeMemory32(0x00008000 | 0, 0x01E1A128, "Memory"); // PLL1->POSTDIV = DIV_ENABLE | postdiv (0+1);

   // spin until all transitions are complete.
   while (TESTBIT(0x01E1A13C, 0x00000001)) {} // while (CHKBIT(PLL1->PLLSTAT, GOSTAT)) {}

   // program the divisors.
   __writeMemory32(0x00008000 | 0, 0x01E1A118, "Memory"); // PLL1->PLLDIV1 = DIV_ENABLE | plldiv1;
   __writeMemory32(0x00008000 | 1, 0x01E1A11C, "Memory"); // PLL1->PLLDIV2 = DIV_ENABLE | plldiv2;
   __writeMemory32(0x00008000 | 2, 0x01E1A120, "Memory"); // PLL1->PLLDIV3 = DIV_ENABLE | plldiv3;

   // kick off the transitions and spin until they are complete.
   SETBIT(0x01E1A100, 0x00000001); // SETBIT(PLL1->PLLCMD, GOSET);
   while (TESTBIT(0x01E1A13C, 0x00000001)) {} // while (CHKBIT(PLL1->PLLSTAT, GOSTAT)) {}

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   __delay(10);

   // bring pll out of reset and wait for pll to lock.
   SETBIT(0x01E1A100, 0x00000008); // SETBIT(PLL1->PLLCTL, PLLRST);
   __delay(10);

   // exit bypass mode.
   SETBIT(0x01E1A100, 0x00000001); // SETBIT(PLL1->PLLCTL, PLLEN);

   // lock pll regs.
   SETBIT(0x01C14188, 0x00000020); // SETBIT(SYSCONFIG->CFGCHIP[3], PLL1_MASTER_LOCK);
}

SetupPSC()
{
  __message "Executing PSC setup\n";

   //-----------------------------------------
   // PSC0, domain 0 - all modules, always on.
   //-----------------------------------------

   // configure the next state for psc0 modules.

   lpsc0Enable(1, 3,  3);
   lpsc0Enable(1, 4,  3);
   lpsc0Enable(1, 5,  3);
   lpsc0Enable(1, 6,  3);
   lpsc0Enable(1, 9,  3);
   lpsc0Enable(1, 10, 3);
   lpsc0Enable(1, 11, 3);
   lpsc0Enable(1, 12, 3);

   //-----------------------------------------
   // PSC1, domain 0 - all modules, always on.
   //-----------------------------------------

   // configure the next state for psc1 modules.

   lpsc1Enable(1, 1,  3);
   lpsc1Enable(1, 2,  3);
   lpsc1Enable(1, 3,  3);
   lpsc1Enable(1, 4,  3);
   lpsc1Enable(1, 5,  3);
   lpsc1Enable(1, 7,  3);
//    lpsc1Enable(1, 8,  3);
   lpsc1Enable(1, 9,  3);
   lpsc1Enable(1, 10, 3);
   lpsc1Enable(1, 11, 3);
   lpsc1Enable(1, 12, 3);
   lpsc1Enable(1, 13, 3);
   lpsc1Enable(1, 14, 3);
   lpsc1Enable(1, 15, 3);
   lpsc1Enable(1, 16, 3);
   lpsc1Enable(1, 17, 3);
   lpsc1Enable(1, 18, 3);
   lpsc1Enable(1, 19, 3);
//    lpsc1Enable(1, 20, 3);
//    lpsc1Enable(1, 24, 3);
//    lpsc1Enable(1, 25, 3);
//    lpsc1Enable(1, 26, 3);
    lpsc1Enable(1, 31, 3);

}


SetupPLLs()
{
  __message "Executing PLLs setup\n";
  SetupPLL0();
  SetupPLL1();

	
}

SetupDDRRAM()
{
  __message "Executing DDRRAM setup\n";

	
  // unlock the system config registers and set the ddr 2x clock source.
	__writeMemory32(0x83E70B13, 0x01C14038, "Memory"); // SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
	__writeMemory32(0x95A4F1E0, 0x01C1403C, "Memory"); // SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;

	CLRBIT(0x01C14188, 0x00000080); // CLRBIT(SYSCONFIG->CFGCHIP[3], CLK2XSRC);

  // enable emif3a clock.
  lpsc1Enable(1, 6,  3);	// EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_ENABLE);

	// check if vtp calibration is enabled.
	if (TESTBIT(0x1E2C0000, 0x00000040))
	{
		// vtp cal disabled, begin cal.
    // enable input buffer and vtp.
    SETBIT(0x1E2C0000, 0x00004000); // SETBIT(VTPIO_CTL, 0x00004000);
    CLRBIT(0x1E2C0000, 0x00000040); // CLRBIT(VTPIO_CTL, 0x00000040);

    // pulse clrz to init vtp cal.
    SETBIT(0x1E2C0000, 0x00002000); // SETBIT(VTPIO_CTL, 0x00002000);
    CLRBIT(0x1E2C0000, 0x00002000); // CLRBIT(VTPIO_CTL, 0x00002000);
    SETBIT(0x1E2C0000, 0x00002000); // SETBIT(VTPIO_CTL, 0x00002000);

    // poll ready bit to wait for cal to complete.
    while (!TESTBIT(0x1E2C0000, 0x00008000)) {}

    // set lock and power save bits.
    SETBIT(0x1E2C0000, 0x00000180); // SETBIT(VTPIO_CTL, 0x00000180);
	}

	// config ddr timing.
	__writeMemory32(0x000000C4, 0xB00000E4, "Memory"); // DDR->DDRPHYCTL1 = 0x000000C4;
	__writeMemory32(0x0893C622, 0xB0000008, "Memory"); // DDR->SDCR = 0x0893C622;
	CHGBIT(0xB0000008,0x00F00000,0x00800000);	// DDR->SDCR &= ((DDR->SDCR & 0xFF0FFFFF) | 0x00800000);
	CHGBIT(0xB0000008,0x00F00000,0x02000000);	// DDR->SDCR = ((DDR->SDCR & 0xFF0FFFFF) | 0x02000000);
	CLRBIT(0xB0000008,0x00008000); // DDR->SDCR &= (~0x00008000);
	
	__writeMemory32(0x20923A89, 0xB0000010, "Memory"); // DDR->SDTIMR1 = 0x20923A89;
	__writeMemory32(0x0015C720, 0xB0000014, "Memory"); // DDR->SDTIMR2 = 0x0015C720;
	__writeMemory32(0x00000492, 0xB000001C, "Memory"); // DDR->SDCR2 = 0x0;
	__writeMemory32(0x000000C4, 0xB000000C, "Memory"); // DDR->SDRCR = 0x00000492;
	
	// set ddr2 to sync reset.
	SETBIT(0xB000000C, 0xC0000000); // SETBIT(DDR->SDRCR, 0xC0000000);
	
	// sync reset the ddr clock.
	lpsc1Enable(1, 6,  1);	// EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_SYNCRESET);
	
	// enable the clock.
	lpsc1Enable(1, 6,  3);	// EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_ENABLE);
	
	// disable self refresh.
	CLRBIT(0xB000000C,0xC0000000); // CLRBIT(DDR->SDRCR, 0xC0000000);
}

execUserPreload()
{
__var Reg;
  __message "Executing user preload macro\n";
  __hwReset(0);
  // Disable MMU and enable ICache
  Reg = __jtagCP15ReadReg(1, 0, 0, 0);
  Reg &= 0xFFFFFFFA;
  Reg |= 1<<12;
  __jtagCP15WriteReg(1, 0, 0, 0, Reg);
  __message "Enable I Cache\n";

	SetupPSC();
	SetupPLLs();
  SetupDDRRAM();
}

macro files/AIS-generated configuration code.

I'm attaching AIS configuration file and IAR macro file (as txt file).

Please advise.

Thank you

Andrey Bondarev

over 9 years ago

0 Norman Wong over 9 years ago

Guru 26430 points

No expert at DDR settings. But if you looking for a second set of eyes, a quick comparison shows a few differences. AISGEN on left and IAR on the right
PLL1 Div2=1 -> 2
DDR2 SDCR2=0 -> 0x00000492 (reserved bits are being set)
DDR2 SDTIMR=1c923208 -> 0x20923A89
DDR2 SDTIMR2=3811c700-> 0x0015C720
DDR2 SDRCR=c0000492 -> 0x000000C4
DDR2 SDCR=2034622 -> 0x0A034622
The IAR script enables the clock on more peripherals but that should not affect stability.

0 Shankari G over 9 years ago

TI__Mastermind 43955 points

Hi Andrey,

Is it your Custom board or TI EVM/LCDK boards?

The detailed information on AIS gen tool is given in OMAPL138_Bootloader_apps_note. ( section 5.0 )

With reference to the doc, please do check that the settings of PLL and DDR are done correctly in AIS gen.

Regards,

Shankari

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--------------------------------------------------------------------------------------------------------

0 Andrey Bondarev over 9 years ago in reply to Norman Wong

Prodigy 170 points

Norman

Thank you.

I incorporated differences and will run system to see if it helps

Andrey

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AISgen settings for OMAP L138