McASP Mixed Clock Configuration

Curtis Albrecht

Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hello!

I'm having some trouble starting the MCASP ACLKX on the OMAP-L138. My goal is to use the AHCLKX with a divide-by-1 and output the serial clock to the other devices in the system. From the data sheet, the serial clock would be a direct feed-through of the AHCLKX input signal.

With just the DSP in the circuit, I can configure everything the way that I would like, except changing the AHCLKRCTL register to 0x00000000 - this is to change the HCLKXM bit from 1(default) to 0, telling the ACLKX to use the AHCLKX input as the source to perform the clock divide on.

If I leave HCLKXM as a 0, everything seems to work fine. The serial clock runs, a signal appears on the output pin and I can adjust the divide ratio as I please, the only problem is that this passes the system clock through which is not of a desirable frequency.

The main problem that I feel I am having is getting the serial clock to release from reset after switching the HCLKXM source (the GBLCTL write/read hangs). It seems like the AHCLKX input pin should just be passed through when the clock is in reset, but as soon as that bit is changed, the output pin is held high and stays that way. My understanding is that nothing in the GBLCTL can be latched without a serial clock...but my serial clock seems to be completely stopping.

In spruh77a_omap.pdf, table 25-10 says that there is a restriction on changing HCLKXM, am I missing something here?

Do I have to run through the configuration/initialization once and then adjust with a second pass?

Is there a special reset order that has to be followed when using the mcasp in mixed clock mode?

Could the Mux that switches based on HCLKXM be shot?

Any thoughts would be greatly appreciated.

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

If you choose to configure your high frequency clocks (AHCLKX/AHCLKR) in mixed mode, then the clock would be sourced externally on the AHCLKX/AHCLKR pins and it would divide down to derive the low frequency bit rate clock (ACLKX/ACLKR). As i see from the above post, you have chosen to configure HCLKXM bit from 1 to 0 which is right for mixed mode which indicates the high frequency clock input to McASP are externally sourced and it turn, it divide down appropriately to derive for low frequency bit clocks.

However, there are certain consideration to be followed when you start the high frequency external clocks which are given below and these steps are necessary when you choose high frequency serial clocks:

1. Kindly ensure whether the respective internal high-frequency serial clock dividers are taken out of reset by setting the RHCLKRST bit for the receiver and the XHCLKRST bit for the transmitter in GBLCTL. All other bits in GBLCTL would be held at 0.

2. Please ensure to read back from GBLCTL to ensure the bits which was written are successfully latched in GBLCTL before you proceed.

Like above, there is a procedure to start the low frequency bit clocks (ACLKX/ACLKR) and this can be skipped when the clocks are sourced externally. Please refer step4 & step5 in the section 25.2.4.1.2 in the omapl138 TRM below:

http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

To know more details on how to configure high frequency & low frequency serial clocks, you could refer sections 25.2.2.1 & 25.2.2.2 from the above TRM doc. Kindly ensure the high frequency clocks (AHCLKX/ACLKR) configuration for mixed mode through HCLKXM/HCLKXP/HCLKXDIV and HCLKRM/HCLKRP/HCLKRDIV bits in AHCLKXCTL as well AHCLKRCTL control registers in your code.

Thanks & regards,

Sivaraj K

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0 Curtis Albrecht over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 140 points

Hi Sivaraj, thanks for your response.

I agree with everything that you posted. I have a 24.576MHz external clock that is used on AHCLKX as an input. This is intended to be the high frequency clock and then since I'm operating in mixed clock mode, I want to pass this through a divide-by-1 (as set in ACLKXCTL) and then output it on the ACLKX pin for the slaves in the system to use.

I follow the start-up procedure in TRM 25.2.4.1.2, and I seem to have no trouble when I leave HCLKXM as a 1. The bit clock is output at 24MHz (a second external clock wired to OMAP pin OSCIN) which I believe is routed from AUXCLK.

When HCLKXM is a 1, I allow the HCLKs to come out of reset and confirm the GBLCTL bits. Followed by allowing the XCLK to come out of reset and confirm.

When HCLKXM is a 0, I allow the HCLKs to come out of reset and confirm the GBLCTL bits. Followed by allowing the XCLK to come out of reset, but it never does. I hang at this point and the XCLK never starts running.

Thanks again for any advice!

Here is the configuration I have loaded: With the AHCLKRCTL and AHCLKXCTL lines commented out, everything works (uses the internal clock), with them uncommented, it hangs at while (!CHKBIT(MCASP->GBLCTL, XCLKRST)){}

MCASP->GBLCTL = 0;

MCASP->RMASK = 0xFFFFFFFF; // all 32-bits NOT masked
MCASP->RFMT = 0x0001807C; // MSB first, align left, slot=16bits, 1-bit delay, ROR 16-bits
MCASP->AFSRCTL = 0x00000112; // int'l gen'd, FS/word, 2 SLOT TDM = I2S
MCASP->ACLKRCTL = 0x000000A0; // rising edge, clkrm internal, /1 CLKRDIV
//MCASP->AHCLKRCTL = 0x00000000; // HCLKRDIV = 1
MCASP->RTDM = 0x00000003; // SLOT 0 & 1 active I2S
MCASP->RINTCTL = 0x00000000; // ints disabled
MCASP->RCLKCHK = 0x00FF0008; // RMAX = FF, RPS = /256

// configure transmit registers for I2S - all same as above

MCASP->XMASK = 0xFFFFFFFF;
MCASP->XFMT = 0x0001807C;
MCASP->AFSXCTL = 0x00000112;
MCASP->ACLKXCTL = 0x000000A0;
//MCASP->AHCLKXCTL = 0x00000000;
MCASP->XTDM = 0x00000003;
MCASP->XINTCTL = 0x00000000;
MCASP->XCLKCHK = 0x00FF0008;

// config serializers (11 = xmit, 12 = rcv)
MCASP->SRCTL11 = 0x000D; // XMT
MCASP->SRCTL12 = 0x000E; // RCV

// config pin function and direction.
MCASP->PFUNC = 0x00000000;
MCASP->PDIR = 0x14000800;

MCASP->DITCTL = 0x00000000;

MCASP->DLBCTL = 0x00000000;
MCASP->AMUTE = 0x00000000;

USTIMER_delay(1000000);

// enable the audio clocks, verifying each bit is properly set.
SETBIT(MCASP->XGBLCTL, XHCLKRST);
while (!CHKBIT(MCASP->GBLCTL, XHCLKRST)) {}

SETBIT(MCASP->RGBLCTL, RHCLKRST);
while (!CHKBIT(MCASP->GBLCTL, RHCLKRST)) {}

SETBIT(MCASP->XGBLCTL, XCLKRST);
while (!CHKBIT(MCASP->GBLCTL, XCLKRST)){}

MCASP->XSTAT = 0x0000FFFF; // Clear all
MCASP->RSTAT = 0x0000FFFF; // Clear all

SETBIT(MCASP->XGBLCTL, XSRCLR);
while (!CHKBIT(MCASP->GBLCTL, XSRCLR)) {}
SETBIT(MCASP->RGBLCTL, RSRCLR);
while (!CHKBIT(MCASP->GBLCTL, RSRCLR)) {}

MCASP->XBUF11 = 0;

SETBIT(MCASP->XGBLCTL, XSMRST);
while (!CHKBIT(MCASP->GBLCTL, XSMRST)) {}
SETBIT(MCASP->RGBLCTL, RSMRST);
while (!CHKBIT(MCASP->GBLCTL, RSMRST)) {}

SETBIT(MCASP->XGBLCTL, XFRST);
while (!CHKBIT(MCASP->XGBLCTL, XFRST)) {}
SETBIT(MCASP->RGBLCTL, RFRST);
while (!CHKBIT(MCASP->RGBLCTL, RFRST)) {}

while(1);

0 Brad Griffis over 9 years ago in reply to Curtis Albrecht

TI__Guru*** 125430 points

What is the value of the PINMUX0 (01C1 4120h) register? Have bits 23:20 been set to 0001b?

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McASP Mixed Clock Configuration