OMAP-L137 : UART BOOT WITH 25MHz CLK source

Thank you for your prompt reply.

Our customer would like to make sure why there is limitation of input clock source of 24.000MHz in spite of UART can operate properly using 25.000MHz clock.

Their board is so small that they can't put additional clk.

Could you provide what is risk with input clock source of 25.000MHz ?

Your reply would be appreciated.

Hi Senthil

Our customer succeeded UART boot with input clock source of 25 MHz.

Could you make sure attached file that shows wave form when UART boot succeeded?

Your help would be appreciated.
Thanks and best regards.

UART BOOT WITH INPUT CLOCK SOURCE OF 25MHz.xlsx

Hi Senthil

Our customer will change input clock source from 25MHz to 20MHz since 25MHz input clock source doesn't meet specification of F28377D.

Therefore they will change baudrate to 9600.

They think there are no problem since PLL and divider value is not changed from default setting.

Do you have something update?

Your reply would be appreciated.
Thanks and best regards.

Hello Alpha,

As far as you are meeting standard UART baud rate listed in Table 31-1 in device TRM, that should be fine.

Regards,
Senthil

Thank you for your prompt reply.

I would like to confirm about your answer.
In my understanding there are no risk and problem using UART boot with input clock source 20MHz and 9600 baud.

Is my understanding correct?

If you can find the reason why there are limitations of input clock source , please let me know.

Your reply would be appreciated.
Thanks and best regards.

Hello Alpha,

I am working internally to confirm the input clock frequency restriction for UART boot. I will update you once i get a response.

Regards,
Senthil

Hello Senthil

Could you give me your comment for my question about restriction for UART boot?
Because our customer want to fix to their design by this weekend.

Your reply is very important for our customer.

Thanks and best regards.

Hello Alpha,

Here is the response from the internal team regarding the input clock for UART boot.

The bootloader application notes for this device is correct regarding the input frequency to use for UART boot. Only 24 Mhz is supported on OMAPL137/C6747 devices.

The UART boot has 2 stages, the first stage has the device is in bypass state and the second stage starts after the user has configured the PLL. With 25 Mhz input clock, users could set UART to 115200 bps in the second stage by manipulating the PLL multipliers and dividers but the problem is in the first stage when PLL are in bypass, where the bootROM uses hard coded multipler and dividers to get to the 115200 bps.

This issue was fixed in OMAPL138 BootROM as we provided additional boot switch settings to allow users to change the frequency. Look at section 9.2 in OMAPL138 bootloader application notes for other supported input frequencies.

Regards,
Senthil

Hello Senthil

Thank you for your reply.
In my understanding,the reason of restriction is hard coded multipliers and dividers.
Is my understanding correct?

If my understanding is correct,I think UART boot is supported using input clock source of 24MHz with baud rate 9600 bps.

Our customer does not change the frequency.

Your reply would be appreciated.

Thanks and best regards.

Hello Senthil

Thank you for your reply.
In my understanding,the reason of restriction is hard coded multipliers and dividers.
Is my understanding correct?

If my understanding is correct,I think UART boot is supported using input clock source of 24MHz with baud rate 9600 bps.

Our customer does not change the frequency.

Your reply would be appreciated.

Thanks and best regards.

Hello Alpha,

Yes, your understanding is correct. The restriction is due to hard coded multipliers and dividers.

The UART boot is only supported using input clock source of 24MHz. Please refer section 9 Boot Requirements, Constraints and Default Settings in SPRAB04G for default baud rates.

Regards,
Senthil

Hello Senthil
Thank you for your prompt reply.

I would like to reconfirm your comment.

you mentioned input clock source of 24 MHz is needed to get to the 115200 bps.

The reason is bootROM use hard coded multipliers and dividers.
In other words , resistors value of multipliers and dividers are fixed.

If the above is correct,our customer think they can change input clock source with changing UART baud rate.

Please let me know why there is restriction for input clock source.

* Customer's requirement
Input clock source : 24 MHz
UART baud rate : 9600 bps

Thanks and best regards.

Hello Alpha,

The reason behind this restriction is hard coded multipliers and dividers. we have tested the UART boot with 24MHz input clock and the baud rates are mentioned in the bootloader document. We might have faced boot issues for other clock and baud rates. There are certain limitations you should follow for reliable operation of the device.

If you want to operate at 9600bps, you could make a try. It is up to your own risk and we cannot guarantee the reliability.

Regards,
Senthil

Hello Senshil

Thank you for your reply.

Our customer have additional question to consider the risk.
Could you please provide values of PLL multipliers , UART dividers and UART oversampling?

They will configure UART baud rate and input clock source adapted above the values.

Your reply would be appreciated.
Thanks and best regards.

Hello Senthil

I know you are very busy but could you please reply to my question?

Your reply would be much appreciated.
Thank you and best regards.

Hello Alpha,

I do not aware of the hard coded multiplier and divider values. I will try to get this information from internal team.

Regards,
Senthil

Hello Sentil

 I know you are very busy but could you please reply to my question?

Your reply is very important for our customer to assume their risks.

Thank you and best regards.

Hi Alpha,

Yes, the bootloader application notes for this device is correct regarding the input frequency to use for UART boot. Only 24 Mhz is supported on OMAPL137/C6747 devices in the BootROM.

The UART boot has 2 stages, the first stage has the device in bypass state and the second stage starts after the user has configured the PLL. With 25 Mhz input clock, users could set UART to 115200 bps in the second stage by manipulating the PLL multipliers and dividers but the problem is in the first stage when PLL are in bypass, where the bootROM uses hard coded multipler and dividers to get to the 115200 bps.

If the usecase doesn`t involve UART boot then the device can use 25Mhz clock as the issue with hard coding of values only exists in the BootROM.

This issue in the BootROM was fixed in OMAPL138 BootROM as we provided additional boot switch settings to allow users to change the input frequency. Look at section 9.2 in OMAPL138 bootloader application notes for other supported input frequencies.

Hope this answers your question.

Regards,
Rahul

PS: USe the PLL clocking spreedsheet here to simulate the clocks to get required Baudrates:

 

Hello Rahul

Thank you for your reply.

I understand OMAPL137 needs 24 MHz input clock to get to the 115200 bps.

Can our customer change baud rate ?

For example , If they changed baud rate 96000 bps with 20 MHz input clock , I think divide ratio become same as application note.

Input clock source 24 MHz -> 20 MHz (ratio 5/6)
Baud rate 115200 bps -> 96000 bps (ratio 5/6)

If the device is not supported to change baud rate could you please tell the reason.
Your reply would be appreciated.

Thanks and best regards.

Here is the piece of code in the bootROM for your reference.

// 13x over sampling
hUARTRegs->MDR = 0x01;

// Set DLAB bit - allows setting of clock divisors
hUARTRegs->LCR |= 0x80;
UTIL_waitLoop(100);


// Baud clock generator
// Divisor value = cba_clk / (13x baud rate) [osr_sel=1]
// Assumed:
// Input Freq = 24 MHz
// PLL in bypass, so CPU = 24 MHz
// SYSCLK2 = CPU / 2 = 12 MHz
// Baud rate is 115200
// uartDiv = Divisor = 12000000/ (115200 *13) = 8 (rounded to closest decimal)
hUARTRegs->DLL = uartDiv & DEVICE_UART_DLL_MASK;
hUARTRegs->DLH = (uartDiv>>8) & DEVICE_UART_DLH_MASK;

So the UART divider is set to 8 and the oversampling is set to 13. Given this assumption if you use a 20Mhz input clock then the resulting baud rate will be

//Input Frequency = 20Mhz
// PLL in bypass so CPU =20Mhz
//SYSCLK2 = 10Mhz
// Divisor = 8

Resulting baud rate will be = 10000000/ (8*13) = 96153

Since it will not resulting in a standard baud rate, we have some concerns regarding the data transfer over UART.

Let us know if you have any feedback questions regarding this issue.

Regards,
Rahul