Hello,
I have a custom OMAPL138 based board which has a 256MB Micron nand flash (MT29F2G08AAC). I use the same connections as the L138 EVM UI board.
I use the kernel from arago git tree. (http://arago-project.org/git/projects/?p=linux-omapl1.git;a=summary)
I am trying to optimize the nand read/write performance on my custom board.
I have the following timings in my board file.
static struct davinci_aemif_timing atlas_nandflash_timing = {
.wsetup = 0,
.wstrobe = 30,
.whold = 30,
.rsetup = 10,
.rstrobe = 20,
.rhold = 10,
.ta = 0,
};
static struct davinci_nand_pdata atlas_nandflash_data = {
.parts = atlas_nandflash_partition,
.nr_parts = ARRAY_SIZE(atlas_nandflash_partition),
.ecc_mode = NAND_ECC_HW,
.ecc_bits = 4,
.options = NAND_USE_FLASH_BBT,
.timing = &atlas_nandflash_timing,
};
CPU is working at 300MHz and EMIFA_CLK is 100MHz.
With these values, i have aproximately 7MB/s read speed from the nand device
I use the following command to check read speed:
# time dd if=/dev/mtd5 of=/dev/zero bs=2048 count=5000
5000+0 records in
5000+0 records out
real 0m 1.45s
user 0m 0.01s
sys 0m 1.42s
But when i check the actual nand timings with a scope i realize an interesting issue.
Here is the screenshot of a typical nand read cycle:
CH1 is the nand chip enable (_CE) signal which is routed from L138's EMA_CSn_3 pin.
CH2 is the nand read enable (_RE) signal which is routed from L138's EMA_OEn pin.
Time scale is 100ns/div
As it is seen from the attached screenshot, there is some delay between each 4 byte read from the nand device.
Between these 4-byte read cycles, chip enable signal goes high.
I think because of this delay davinci nand driver is not working at its full speed.
I searched davinci nand driver source but can not find an explanation to this situation.
The question is:
Where was this delay come from? Is it possible to minimize this delay?
Regards,
Alper
