OMAPL138B-EP: Are channels associated with reserved sync events on EDMA3 Channel Controller 1 safe to use?

Patrick McCloskey said:

I interpret this table to indicate there are no peripheral interface events that will trigger synchronization events for channels 19, 20, 21, 22, 23,  and 30, 31 on EDMA3 Channel Controller 1.

Correct.

Patrick McCloskey said:

Is it safe to use those channels (19, 20, 21, 22, 23,  and 30, 31) from EDMA3 Channel Controller 1 for chained transfers or "manually" triggered transfers?

Yes.  Those are ideal channels to use for that purpose since you don't give up some other peripheral event.

Patrick McCloskey said:

Would you expect things to work out for me if I used a hardware interrupt on a GPIO line in bank 8 to fire EDMA3 Channel Controller 1 synchronization event 18 (GPIO Bank 8 Interrupt) to trigger a transfer on EDMA3 Channel Controller 1 channel 18, which then triggers chained transfers on channel 19, then 20, then 21, etc.?

That's fine in terms of the general event mapping and usage.  You'll have to be careful about using GPIO Bank 8 for anything else though.  In particular, you don't want to have any other interrupts that are connected to Bank 8.

As a quick example, let's say that in your system you have two external interrupt sources:

1. The first source you want to initiate a DMA event.  You hook this up to one of the GPIO Bank 8 pins.
2. The second source you want to initiate a CPU interrupt.  You must hook this up to any pin in Bank 0-7, but it is critical to avoid Bank 8.

If you hook up more than one interrupt to Bank 8, then your EDMA event will run in response to all of them.  In other words, there's no way to get the EDMA controller to go check the Bank 8 INTMUX register and only respond in the case where a specific bit is set.

You can still use Bank 8 for general purpose inputs and outputs.  You just can't use it for any other INTERRUPTS or else the EDMA will respond to all of them.

Also, in order to get additional Bank 8 interrupts to generate EDMA events it will be necessary to clear out the event from the INTSTAT register of Bank 8.  Since the INTSTAT register is a "write 1 to clear" register you could conceivably have a word sitting in memory that has been predefined with the appropriate bit set for clearing your event.  As part of this whole chaining process you could chain once more such that the EDMA takes that pre-defined word and writes it to the INTSTAT register to clear out the pending interrupt.