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Starterware/OMAPL138B-EP: OMAPL138 EDMA3_1_CC0 problem

Part Number: OMAPL138B-EP
Other Parts Discussed in Thread: OMAP-L138

Tool/software: Starterware

Hello!

I'am using StarterWare and trying to use EDMA3_1_CC0 channel controller to read/write flash through SPI0 interface.

Everything works fine with EDMA3_0_CC0.

With EDMA3_1 no EDMA interrupts occured...

Trying to debug situation...

after SPIIntEnable(...) rises corresponding bit in ER (event register), but in EDMACC0DSP register group (view registers in debug window).

As i understand this bit should be in EDMACC1DSP group, because i used SOC_EDMA31CC_0_REGS only. So no EDMA3 interrupt occured.

Can  anybody help?

  • Simple DDR memory transfer works well with EDMA3_1_CC0 (but without interrupt generation (no EDMA3CC_OPT_TCINTEN)).

  • Moving this thread to the L138 forum.
  • No expert on EDMA. It is a very complex peripheral. It would appear that each channel controller has specific events mapped to it. For example, SPI0 is mapped to CC0 only and is not accessible by CC1.

    StarterWare defines these events in edma_event.h. Example overlap of events:

    /* SPI0 Receive Event */
    #define EDMA3_CHA_SPI0_RX 14
    /* SPI0 Transmit Event */
    #define EDMA3_CHA_SPI0_TX 15
    /* SPI1 Receive Event */
    #define EDMA3_CHA_SPI1_RX 18
    /* SPI1 Transmit Event */
    #define EDMA3_CHA_SPI1_TX 19

    /* Timer 3 compare event6 (TPCC1) */
    #define EDMA3_TIMER3_T12CMPEVT6 14
    /* Timer 3 compare event7 (TPCC1) */
    #define EDMA3_TIMER3_T12CMPEVT7 15

    The code is gives a subtle hint about CC1 events with a "(TPCC1)" in the comment line above the define.

    I guess DDR memory transfers doesn't support events.

    Reference:
    SPRS586J OMAP-L138 Datasheet
    6.9.1 EDMA3 Channel Synchronization Events
    Table 6-14. EDMA Synchronization Events
  • Effectively reconfirming what Norman said. If you are using EDMA to transfers to/from SPI using SPI DMA events, these events are only hooked to CC0 and there CC0 and its associated TCs need to be used for these transfers.
    So please look at the tables Norman pointed to , to see which peripheral events are routed (hardwired in architecture) to which CC.
  • Yes. Thank you very much!