I am currently using an OMAP3530 with an 8bit video decoder chip (MAX9526) and trying to configure the ISP interface on our OMAP processor to write YUV422 to memory without any resizers filters etc.
However, I only continuously get an event (HS_VS_IRQ), but some interrupts(CCDC_VD0_IRQ and CCDC_VD1_IRQ) was called few times after CCDC_PCR[0] is set. And no data was written to memory.
In my application program, I allocated memory(720 x 480 *2 bytes) for YUV data and assign address pointers to the CCDC_SDR_ADDR register.
Some questions confusing me much are as follows:
1. Should I use CBUFF and SBL for bypass from CCDC to memory? If yes, could some tell me how to set them?
2. Once receiving CCDC_VD0_IRQ or CCDC_VD1_IRQ, does it mean a frame is done and I can access the frame buffer?
3. In ITU-R BT.656(NTSC) mode, how does isp counts lines to reach VDINT?
Also I hope someone could help me review my settings:
// Set the clocks for the Camera ISP module
*CM_CLKSTCTRL_CAM = 0x00000002; // Wake from sleep
*PM_WKDEP_CAM = 0x00000016; // Enable wake-up domain (both IVA and MCU)
// DPLL4 = (SYCLK/2) x 2 x M/N + 1 => 13 x 2 x 432/12 + 1 = 864 MHz
*CM_CLKSEL_CAM = 0x00000004; // cam_mclk = 216 MHz(864 / 4 = 216 MHz)
*CM_FCLKEN_CAM = 0x00000001; // enable cam_fclk/cam_mclk
*CM_ICLKEN_CAM = 0x00000001; // enable cam_iclk
*CM_SLEEPDEP_CAM = 0x00000000; // not in MPU mode
*PM_PWSTCTRL_CAM = 0x00000003; // powerstate = on
// Wait until ISP reset is done
ISP_SYSCONFIG = 0x00001002; // standby = never, perform a software reset
while( !(ISP_SYSSTATUS & 0x00000001) ) {
TSK_sleep(1);
}
ISP_IRQ0STATUS = 0xFFFFFFFF;
ISP_IRQ1STATUS = 0xFFFFFFFF;
ISP_TCTRL_CTRL = 0x00000000;
ISP_TCTRL_FRAME = 0x00000000;
ISP_IRQ0ENABLE = 0xB2200F00;
// timing control
TCTRL_CTRL = 0x00000000;
TCTRL_FRAME = 0x00000000;
// disable all other features/submodules of the Camera ISP
CCP2_CTRL = 0x00000000;
CCP2_SYSCONFIG = 0x00000000;
CCP2_LC01_IRQENABLE = 0x00000000;
CCP2_LC23_IRQENABLE = 0x00000000;
HIST_PCR = 0x00000000;
H3A_PCR = 0x00000000;
PRV_PCR = 0x00000000;
RSZ_PCR = 0x00000000;
CSI2_CTRL = 0x00000000;
CSI2_SYSCONFIG = 0x00000000;
CSI2_IRQENABLE = 0x00000000;
CCP2_SYSCONFIG = 0x00000000;
CCP2_LC01_IRQENABLE = 0x00000000;
CCP2_LC23_IRQENABLE = 0x00000000;
SBL_PCR = 0x07FF0000; // clear SBL errors
// set up the control register
// - Select parallel port as input port (PAR_SER_CLK_SEL=0, PAR_BRIDGE=0)
// - Sample data on the rising edge of cam_pclk (PAR_CLK_POL=0)
// - Do not shift the data (SHIFT=0)
// - Enable CCDC
// - Disable CBUFF autogating feature
// - Disable H3A, HIST, PRV, RSZ submodules
// - Set SYNC_DETECT to VSync rising edge for interrupt
// - All other features are disabled
ISP_CTRL = 0x2001C100;
// set up CCDC
// - select SYNC mode, HS, VS and FLD (not used) are inputs
// - polarity: active high (positive)
// - 8-bit data
// - module accepts YUV input data, w/o filtering and what not
// - set internal timer generator to sync with VSync and HSync
// - enable writes to memory
CCDC_SYN_MODE = 0x00032F00;
CCDC->REC656IF = 0x00000003;
// - set WENLOG (I'm sure it should be or not)
// - set VDLC
CCDC_CFG = 0x8100;
// Set horizontal offset (when 0 each line will be overwritten)
CCDC_HSIZE_OFF = 0x000005A0; // 720 pixels
// set initial address
CCDC_SDR_ADDR = (Uint32)(&(framebuffer[0])); // allocated by me
// Pixels/lines to mem
CCDC_HORZ_INFO = 0x000002CF; // 719+ 1 pixels to memory
CCDC_VERT_LINES = 0x000001DF; // 479 + 1 lines to memory
CCDC_VERT_START = 0x00000000;
// disable all other features
CCDC_CULLING = 0xFFFF00FF; // default values: retain all pixels
CCDC_SDOFST = 0x00000000;
// disable all other features of the CCDC
CCDC_CLAMP = 0x00000000;
CCDC_ALAW = 0x00000000;
CCDC_FMTCFG = 0x00000000; // disable PREVIEW, H3A and HIST
CCDC_LSC_CONFIG = 0x00000000; // disable lens-shading compensation
// set intterrupt
CCDC_VDINT = 0x00EF00EF; // VDINT0 After 1024 + 1 lines, VDINT1 after 0 lines (not enabled)
// enable CCDC (can only be done after it has been configured)
CCDC_PCR = 0x00000001;