Setting Vector Table high for OMAP35xx

I'm usually used to the MMU enabled and virtual FFFF0000 mapped to some location in SDRAM.  What you might want to try is to locate your execption vectors to SRAM.  There is a ROM in OMAP35x that starts at location 0x00000000 and ends somewhere else.  Looking at the TRM, when the MMU is disabled, the exception vectors in ROM will jump to vectors in SRAM.

Undefined is at 0x4020FFC8

SWI is at 0x4020FFCC

Prefetch Abort is at 0x4020FFD0

Data Abort is at 0x4020FFD4

Unused 0x4020FFD8

IRQ 0x4020FFDC

FIQ 0x4020FFE0

Thanks for you support.

In Cortex A8 , there is a provision for reloacating the vector to an address of your choice.

I have worked in ARM 9 and this feature was not there in ARM 9. Now i understand we can relocate to any address of our choice by writing into c 12 register (Vector Base register).

Now the Problem is solved..

Hi Jack, Greetings!!

I am trying to relocate the Vector Table on the OMAP 3530 from Address 0x00000000 (GPMC Area) to 0x40200000 (Internal SRAM). The MMU is Enabled.

I would like some input on writing into c 12 register (Vector Base register) as mentioned in your above post. Please provide some input.

Regards, Abel.

Hi Abel,

You can relocate the Vector base to any address of your choice.

 ; set Vector base address to be 0x8000:0000
    mov    r0,  #0x80000000
    mcr    p15, #0, r0, c12, c0, #0

in the above case the vector table is relocated to 0x80000000. 

In your case it would be 0x40200000.

Thanks

Jack

Thanks Jack,

I was able to relocate the Vector table to the Internal SRAM.

Regards,

Abel

Hi Steve

When i follow the TRM for the OMPA35xx and would like to overwrite the "dead loop handler" for a software interrupt, i have to do the following (my code is located in SDRAM starting from address 0x8000 0000).

Example:

// RAM exception vectors
 // In 0x4020FFCC is the Assembler Instruction: LDR PC,0x4020 FFE8
 *(unsigned int volatile *)0x4020FFCC = 0xE59FF014;
 // In 0x4020FFE8 is the address of my Software Interrupt Handler (in this example at the address 0x8000 0b50)
 *(unsigned int volatile *)0x4020FFE8 = (unsigned int)&MY_SWI_HANDLER;

Let's assume i generate a software exception, the callstack looks like this:

1. Software interrupt generated
   0x80000C78:   EF000002 SWI             #2
2. It jumps to the ROM SWI exception handler at address 0x14008 where the PC is set to the address stored in 0x14028
   0x00014008:   E59FF018 LDR             PC, 0x14028
3. Context of 0x14028
   0x00014028:   4020FFCC
4. Now the PC points to 0x4020FFCC, which i did modify in my code
   0x4020FFCC:   E59FF014 LDR             PC, 0x4020FFE8
5. This will set the PC to address stored in 0x4020FFE8, which is my software interrupt handler
   0x4020FFE8:   80000B50
6. Finally, the code reaches my software interrupt handler

So far so good. The big difference to the TRM is, i had to fill the 0x4020FFCC register manually.
Table 25-10 in the SPRUF98K claims, that 0x4020FFCC contains the following, but it's wrong:
 

Questions:

1. This program flow generates two additional instructions before my ISR is invoked, isn't there a more elegant way to define the interrupt vector table?
2. I tried to compile the assembler example above (to relocate the vector base) with Code Composer v4.2.1 TMS470, but failed with the following error:
   
   ERROR!   at line 4: [E0004] Immediate cannot be greater than 16-bits
   MOV r0, #0x4020FFCC
   
   Assembler code:
    .global _relocateVectorBaseRAM
   _relocateVectorBaseRAM:
       ; set Vector base to the RAM exception table
       MOV  r0, #0x4020FFCC
       MCR  p15, #0, r0, c12, c0, #0
       BX lr 
3. What's the correct adress to relocate the exception vector for the OMAP35? Is 0x4020FFCC correct?
4. Since the ARM Assembly Syntax and the TI Assembly Syntax are different (see comment), where can i find the syntax for the TI Assembly Language?

MGun said:

 

1. ERROR!   at line 4: [E0004] Immediate cannot be greater than 16-bits
   MOV r0, #0x4020FFCC
   
   Assembler code:
    .global _relocateVectorBaseRAM
   _relocateVectorBaseRAM:
       ; set Vector base to the RAM exception table
       MOV  r0, #0x4020FFCC
       MCR  p15, #0, r0, c12, c0, #0
       BX lr 
2. What's the correct adress to relocate the exception vector for the OMAP35? Is 0x4020FFCC correct?

 

u cannot give "MOV  r0, #0x4020FFCC" as single instr as it will be greater than 32 bits.

ARM has fixed instruction size. max size is 32 bits.

You need to  use barrel shifter to input a 32bit value into the r0.

for eg:

    mov r5, #0x40
    mov r0, r5, lsl#24   ; we left *** r5 by 24 bits, then save that value into r0
    mov r5, #0x20        ; r5 = 0x20
    mov r5, r5, lsl#16   ; we left shift r5 by 15bits and save the value into r5 itself
    orr r0, r0, r5             ; logical OR r0 and r5 and save the result in r0.

r0 will now contain 0x40200000