Problem Enabling RMII interface on NDK EMAC driver

Jimmy Setyo42

Intellectual 310 points

Other Parts Discussed in Thread: TMS320C6455, SYSBIOS

Here is my Hardware setup:

TMS320C6455 (EMAC MII port) <---- (MII port) ---->[ Enet Switch ] <--- (RMII port) --> Host P1021 (MAC RMII port)

MDIO port on the switch is controlled by the Host. There is no MDIO connection between DSP and the enet switch.

I am using NDK 2.24.00.11 + C6455 driver and sysbios 6.31.04.27.

I was be able to successfully passing message back and forth via TCP/IP socket between Host and DSP.

Then I modified DSP <--> Enet switch connection from MII to RMII, made some modification on the C6455 driver, and my socket connection is no longer working.

Here are some modification on the C6455 driver that I made:

In the EMAC_open in csl_emac.c, I added the following

CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIISPEED, 25MHZ);

CSL_FINST(EMAC_REGS->MACCONTROL, EMAC_MACCONTROL_RMIIDUPLEXMODE, FULLDUPLEX);

Then after GMIIEN bit is set, I added the following code to de-assert RMII_RST bit.

CSL_FINS(DEV_REGS->EMACCFG, DEV_EMACCFG_RMIIRST, RELEASE);

The above changes broke my socket connection. Then I noticed several potential issues in the cslr_dev.h. Could someone please clarify this?

Is RMII_RST on bit 19 or bit 18?

RMIIRST_MASK is defined as 0x00080000 <--- Should this be 0x00040000 since RMII_RST is on bit 18?

RMIIRST_SHIFT is defined as 0x00000013 <-- I think this should be 0x00000012 if RMII_RST is on bit 18.

RMIIRST_ASSERT is defined as 0x00000000 <-- assert should be 1 according to datasheet

RMIIRST_RELEASE is defined as 0x00000001 <-- de-assert value should be 0 according to datasheet

After updating the #define values in cslr_dev.h, I still have problem with RMII interface. Please advise.

Thanks.

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

The GMII and RGMII interfaces use different logic than the RMII interface, so they have different clock requirements. The external 50 MHz RMREFCLK is the clock that is used for the RMII interface. I would recommend you to check section 8.11.2.1 for RMII implementation from C6455 design guide as below:

http://www.ti.com/lit/an/spraa89a/spraa89a.pdf

Also, please refer section 2.3.2 for RMII interface connection from the C6455 EMAC/MDIO user guide as below:

http://www.ti.com/lit/ug/spru975e/spru975e.pdf

May be, before asking for NDK support, it would be better to check the below wiki, it would be nice:

http://processors.wiki.ti.com/index.php/Before_asking_for_NDK_support

http://processors.wiki.ti.com/index.php/Guidelines_when_porting_NDK_to_different_PHYs#Useful_information

To switch between MII and RMII interfaces, it would be better if you walkthrough the below e2e posts on ethernet forum, you would get a good idea on this:

https://e2e.ti.com/support/interface/ethernet/f/903/t/315750

https://e2e.ti.com/support/interface/ethernet/f/903/t/310855

Thanks & regards,

Sivaraj K

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0 Jimmy Setyo42 over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 310 points

Hi Sivaraj,

Thanks for the reply.

I wasn't used GMII or RGMII interface.

For RMII interface, I supplied both DSP's RMREFCLK (RMII Reference Clock) and Enet Switch's RMII external clock inputs with 50MHz per App note.

I also changed DSP's MACSEL[1:0] to 01 for RMII mode, and I changed Enet Switch's Mode to RMII with external clock.

I checked my hardware connection, it matches with the user guide for RMII connection.

Could someone please clarify whether RMII_RST is on bit 19 or bit 18? According to TMS320C6455's datasheet, it's on bit 18. However C6455 driver updates bit 19.

0 Brad Caldwell over 9 years ago in reply to Jimmy Setyo42

TI__Genius 12595 points

Jimmy,

I was checking the C6455 datasheet and noticed there are MAC_SEL pins (AEA[10:9] pins) that select the MAC mode. If you look closely at the DEVSTAT register definition, the MACSEL filed is read-only, it gets its value from the MAC_SEL pins at reset. I'm wondering if this is your issue. Can you read your DEVSTAT register and tell us what value you read back?

I'll let somebody else confirm the RMII_RST bit position although I tend to trust the datasheet over everything else.

Thanks,

-Brad

0 Jimmy Setyo42 over 9 years ago in reply to Brad Caldwell

Intellectual 310 points

Hi Brad,

I modified AEA[10:9] from MII to RMII. I also checked DEVSTAT earlier. The value I read 0x00400301, which means MACSEL[1:0] = 10 (RMII), and EMAC pin functions are enabled.

Thanks,
Jimmy

0 Jimmy Setyo42 over 9 years ago in reply to Brad Caldwell

Intellectual 310 points

I got this work now. I had to put 1K pulldown on DSP's RMRXER input. I found this information on figure 5 of the following document. This document is for C6472 device.
www.ti.com/.../spraau2a.pdf

Also I need to update C6455 driver that comes with NSP package to fix RMII_RST bit location. The correct bit location for RMII_RST is on EMACCFG[18]. The driver updates EMACCFG[19].

Here are changes I made on c6455/inc/cslr_dev.h:

#define CSL_DEV_EMACCFG_RMIIRST_MASK (0x00040000u) //was 0x00080000u

#define CSL_DEV_EMACCFG_RMIIRST_SHIFT (0x00000012u) //was 0x00000013u

#define CSL_DEV_EMACCFG_RMIIRST_ASSERT (0x00000001u) // was 0x00000000u

#define CSL_DEV_EMACCFG_RMIIRST_RELEASE (0x00000000u) // was 0x00000001u

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Problem Enabling RMII interface on NDK EMAC driver